Custom IC Design

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Discussion

Restrict ICPR SGE Job to only run 1 simulation point (ADE Assembler)

Category: Custom IC Design

By jehh
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updated over 4 years ago by Andrew Beckett

1 replies • 11509 views
Discussion

How can I fix the error in my simulation?

Category: Custom IC Design

By yysunj
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updated over 4 years ago by Andrew Beckett

3 replies • 11960 views
Discussion

Using FinFETs in OrCAD Capture

Category: Custom IC Design

By Sati
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updated over 4 years ago by Sati

2 replies • 10927 views
Discussion

Question on PSS+PNoise simulation for a Track and Hold circuit

Category: Custom IC Design

By YutaoLiu
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updated over 4 years ago by Andrew Beckett

11 replies • 13712 views
Discussion

Post Layout simulation for multi-finger transistors

Category: Custom IC Design

By Senan
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updated over 4 years ago by FormerMember

11 replies • 14805 views
Discussion

noise sim always report 0% of Total

Category: Custom IC Design

By monglebest
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updated over 4 years ago by Andrew Beckett

8 replies • 13206 views
Discussion

Working model for MDL language - A query

Category: Custom IC Design

By MicheleAncis
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updated over 4 years ago by FormerMember

2 replies • 1698 views
Discussion

Adding wreal input and output bus in verilog-AMS

Category: Custom IC Design

By RFStuff
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updated over 4 years ago by RFStuff

5 replies • 15025 views
Discussion

HISIM-HV models

Category: Custom IC Design

By pejmank
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updated over 4 years ago by Andrew Beckett

2 replies • 11259 views
Discussion

Verilog-A white_noise function returns 0 in transient noise simulation

Category: Custom IC Design

By threepwood06
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updated over 4 years ago by threepwood06

4 replies • 11870 views
Discussion

Canceling out the parasitic diode in Layout

Category: Custom IC Design

By Hossein Eslahi
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started over 4 years ago

0 replies • 10884 views
Discussion

Current density check for layout design

Category: Custom IC Design

By Senan
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updated over 4 years ago by Senan

4 replies • 13289 views
Discussion

"ERROR: attempt to access a quantity that depends on the time derivative" in Verilog-A

Category: Custom IC Design

By rhanna
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updated over 4 years ago by Andrew Beckett

13 replies • 5279 views
Discussion

Bindkeys in ADE Explorer/Assembler

Category: Custom IC Design

By crossi
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updated over 4 years ago by crossi

5 replies • 2512 views
Discussion

illegal connection CAD warning message

Category: Custom IC Design

By Senan
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started over 4 years ago

0 replies • 10763 views

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