Custom IC Design

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layout connection problem in virtuoso layout XL

Category: Custom IC Design

By whitefan

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updated over 12 years ago by whitefan

2 replies • 15142 views
Discussion

layout issue while creating contacts

Category: Custom IC Design

By whitefan

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updated over 12 years ago by whitefan

2 replies • 14786 views
Discussion

Virtuoso 6.1.5 warnings issues

Category: Custom IC Design

By djamal

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updated over 12 years ago by djamal

8 replies • 20081 views
Discussion

OCEAN script generated for AMS + APS simulation

Category: Custom IC Design

By alleyor

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updated over 12 years ago by Andrew Beckett

2 replies • 15199 views
Discussion

meassuring delay in viva

Category: Custom IC Design

By jerry124

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updated over 12 years ago by Andrew Beckett

3 replies • 16428 views
Discussion

Power net short error during Verilog import

Category: Custom IC Design

By Kabal

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updated over 12 years ago by Andrew Beckett

1 replies • 15881 views
Discussion

Error with Assura QRC using IBM 0.13um SiGe

Category: Custom IC Design

By sriram123

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updated over 12 years ago by Andrew Beckett

1 replies • 14440 views
Discussion

Monte carlo pre-run script

Category: Custom IC Design

By LinuxMachine

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updated over 12 years ago by Andrew Beckett

1 replies • 15188 views
Discussion

Transistor Finger/Multiplier does not work

Category: Custom IC Design

By EricHsu

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updated over 12 years ago by Andrew Beckett

1 replies • 2322 views
Discussion

Capacitor Mismatch Coefficient for gpdk 180nm technology

Category: Custom IC Design

By indra0804

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updated over 12 years ago by Andrew Beckett

1 replies • 15475 views
Discussion

CMRR of an OP amp

Category: Custom IC Design

By kenambo

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updated over 12 years ago by Andrew Beckett

1 replies • 16844 views
Discussion

Veriloga Montecarlo input from spectre

Category: Custom IC Design

By jeffreyprin

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updated over 12 years ago by Andrew Beckett

1 replies • 14077 views
Discussion

Monte carlo on a verilog A custom macro model based on device instance not subckt instance

Category: Custom IC Design

By Fabb

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updated over 12 years ago by Andrew Beckett

1 replies • 15547 views
Discussion

How do I turn off flighlines from the bulk of transistors....

Category: Custom IC Design

By pham777

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updated over 12 years ago by Andrew Beckett

1 replies • 13949 views
Discussion

Component Display parameter missing in EDIT menu Cadence 6.1.6-64b

Category: Custom IC Design

By sasuke

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updated over 12 years ago by Marc Heise

1 replies • 16646 views

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