Custom IC Design

Latest Posts

Discussion

Netlisting Unsuccessful for PEX Simulation in ADE/ADEXL

Category: Custom IC Design

By shbmsra12

$usertype
•
updated over 3 years ago by shbmsra12

4 replies • 7309 views
Discussion

Segmentation fault upon VerilogA compilation with an if condition

Category: Custom IC Design

By AAbdelRahman

$usertype
•
updated over 3 years ago by AAbdelRahman

4 replies • 8967 views
Discussion

Skill equivalent of "Open design in tab" in Assembler

Category: Custom IC Design

By alexstepanov75

$usertype
•
updated over 3 years ago by alexstepanov75

5 replies • 2056 views
Discussion

How to assign two dimensional bus notation in schematics

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by delgsy

2 replies • 12712 views
Discussion

How to pause a Monte-Carlo simulation run and release license

Category: Custom IC Design

By Svilen64

$usertype
•
updated over 3 years ago by Svilen64

13 replies • 13414 views
Discussion

Is it possible to make the log window line wrap its text?

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by Andrew Beckett

3 replies • 8537 views
Discussion

How to simulate portion of the circuit with pre layout models & remaining circuit with post layout models?

Category: Custom IC Design

By VenkateshTati

$usertype
•
updated over 3 years ago by VenkateshTati

4 replies • 2822 views
Discussion

[Verilog-A/AMS] Using a for loop to instantiate module

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by delgsy

4 replies • 10517 views
Discussion

[SOLVED] [Verilog-A/AMS] Instantiating verilog-ams with analog input and digital output

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 4285 views
Discussion

Can I pass value between runs in Transient Noise simulation?

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by FormerMember

6 replies • 10229 views
Discussion

Assert device check w/ pss.hb

Category: Custom IC Design

By Brad RFeng

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 8734 views
Discussion

Simulating a s-par file created with ADS (advanced methodology)

Category: Custom IC Design

By amitG22

$usertype
•
updated over 3 years ago by amitG22

2 replies • 10585 views
Discussion

Calculator error on arithmetic operation on the reading of digital bus

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by FormerMember

2 replies • 8674 views
Discussion

LayoutXL creating auto connectivity of custom cell

Category: Custom IC Design

By MattTseng

$usertype
•
updated over 3 years ago by Andrew Beckett

5 replies • 8812 views
Discussion

Layout Cannot Show PDK Instance Graph

Category: Custom IC Design

By ovicovic

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 10116 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.