Custom IC Design

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Discussion

Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett

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started over 14 years ago

0 replies • 28913 views
Discussion

Cadence virtuso aging simulation

Category: Custom IC Design

By PB202509293935

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updated 7 hours ago by PB202509293935

4 replies • 310 views
Discussion

How to rerun just one test of a simulation with 2 test and variable dependency

Category: Custom IC Design

By Pedrocasty

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updated 7 hours ago by Yagya Mishra

3 replies • 662 views
Discussion

Creating GaN Device Symbol (EPC2001C) from Spectre Model File in Virtuoso

Category: Custom IC Design

By AT202509281158

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updated 8 hours ago by Yagya Mishra

1 replies • 276 views
Discussion

using output from one point sweep to another

Category: Custom IC Design

By RA202502215244

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updated 9 hours ago by Yagya Mishra

1 replies • 683 views
Discussion

Virtuoso PEX "Nothing in Layout" Issue

Category: Custom IC Design

By AR202509099018

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updated 22 hours ago by Andrew Beckett

3 replies • 209 views
Discussion

Issue with Deselecting Labels Having "Text Drawing" Layers in Layout

Category: Custom IC Design

By AR202509246930

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updated 1 day ago by AR202509246930

4 replies • 267 views
Discussion

can we ask virtuoso to write its lock or CDS.log somewhere else than $HOME ?

Category: Custom IC Design

By ebecheto

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updated 4 days ago by Andrew Beckett

4 replies • 413 views
Discussion

Weird simulation results in latest Spectre Transient Noise Simulation RAK

Category: Custom IC Design

By OPump

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started 4 days ago

0 replies • 231 views
Discussion

calculator expression to compare wreal value with voltage value

Category: Custom IC Design

By Monica123

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updated 4 days ago by Monica123

2 replies • 699 views
Discussion

Having Maestro report what DSPF view it used for each simulation

Category: Custom IC Design

By Mohsen2

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started 5 days ago

0 replies • 132 views
Discussion

ibis2subck for IBIS circuit doesn't extract analogmodel

Category: Custom IC Design

By JoseDuarte

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started 8 days ago

0 replies • 336 views
Discussion

I am not able to select the layer while drawing a wire or a bus in Layout.

Category: Custom IC Design

By skillEater

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updated 8 days ago by RobMan

1 replies • 476 views
Discussion

How to mute WARNING This OS does not appear to be a Cadence supported Linux configuration

Category: Custom IC Design

By ebecheto

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updated 11 days ago by Andrew Beckett

1 replies • 358 views
Discussion

Modgen: How to add dummy FETs sharing diffusion without issues of marker layers?

Category: Custom IC Design

By sceekr

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started 11 days ago

0 replies • 756 views

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