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Custom IC Design

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    Drain & Source are swapped in netlist after Assura RCX!! Help me please!

    Category: Custom IC Design

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    updated over 17 years ago by archive

    2 replies • 6056 views
  • Discussion

    Exporting the DRC marker layer to GDSII

    Category: Custom IC Design

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    started over 17 years ago

    0 replies • 13070 views
  • Discussion

    How can Assura differentiate between drain and source of MOS transistor??

    Category: Custom IC Design

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    updated over 17 years ago by archive

    1 replies • 14198 views
  • Discussion

    How can devices names be assigned during LVS operation??

    Category: Custom IC Design

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    started over 17 years ago

    0 replies • 12555 views
  • Discussion

    Tip of the Week: Create signal sources from sim results

    Category: Custom IC Design

    By archive archive

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    updated over 17 years ago by archive

    1 replies • 15648 views
  • Discussion

    setting default netType property

    Category: Custom IC Design

    By archive archive

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    started over 18 years ago

    0 replies • 13101 views
  • Discussion

    Area measurement in Virtuoso

    Category: Custom IC Design

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    updated over 18 years ago by archive

    3 replies • 14847 views
  • Discussion

    txt mode measurement result (*.mt* *.ms*)

    Category: Custom IC Design

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    updated over 18 years ago by archive

    2 replies • 13404 views
  • Discussion

    A question on result non-consistent between OP and Transient

    Category: Custom IC Design

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    updated over 18 years ago by archive

    3 replies • 13911 views
  • Discussion

    AMS Designer

    Category: Custom IC Design

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    updated over 18 years ago by archive

    2 replies • 13621 views
  • Discussion

    freq_meter component in ahdlLib

    Category: Custom IC Design

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    updated over 18 years ago by archive

    3 replies • 14908 views
  • Discussion

    Tip of the Week: Easily program digital bus values for analog sims

    Category: Custom IC Design

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    updated over 18 years ago by archive

    8 replies • 23682 views
  • Discussion

    inheriting minimum of 2 parent parameters

    Category: Custom IC Design

    By archive archive

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    updated over 18 years ago by archive

    1 replies • 12879 views
  • Discussion

    Handling globals and inherited connections in LVS.

    Category: Custom IC Design

    By archive archive

    •

    updated over 18 years ago by archive

    2 replies • 16697 views
  • Discussion

    add new layer

    Category: Custom IC Design

    By archive archive

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    updated over 18 years ago by archive

    1 replies • 13273 views
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