Custom IC Design

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Discussion

Quantus QRC issue

Category: Custom IC Design

By HY20250821344
•
updated 9 days ago by HY20250821344

2 replies • 605 views
Discussion

Could not find netlist procedure:SpectreFNPairs instance

Category: Custom IC Design

By ranaya
•
updated 10 days ago by Andrew Beckett

5 replies • 745 views
Discussion

LUT implementation using VerilogA code In Cadence Virtuoso

Category: Custom IC Design

By ZulfiqarKiani
•
started 10 days ago

0 replies • 390 views
Discussion

Sorting variables by name alphanumerically in Virtuoso ADE Assembler / maestro

Category: Custom IC Design

By Dominique8765
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updated 11 days ago by Andrew Beckett

1 replies • 218 views
Discussion

sweeping transistor number of fingers in a simulation

Category: Custom IC Design

By TommasoF
•
updated 11 days ago by TommasoF

2 replies • 685 views
Discussion

xrun: *F,SROOTE: Cannot find the Spectre installation

Category: Custom IC Design

By Leo 93
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updated 13 days ago by Andrew Beckett

3 replies • 465 views
Discussion

use DC sweep variable to set another variable

Category: Custom IC Design

By Darrell L
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updated 13 days ago by Darrell L

2 replies • 458 views
Discussion

automate cadence design to avoid time consuming steps for simulation using python subprocess module.

Category: Custom IC Design

By AP202507218251
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started 13 days ago

0 replies • 218 views
Discussion

ERROR (NVN-13010): Cell rupolym is not defined while running Pegasus LVS

Category: Custom IC Design

By yogeshjaiswalCAD
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updated 13 days ago by Andrew Beckett

3 replies • 387 views
Discussion

All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

Category: Custom IC Design

By DavidGogiber
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updated 15 days ago by Andrew Beckett

4 replies • 720 views
Discussion

Cannot Copy Variable to Other Tests

Category: Custom IC Design

By MM202507017815
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updated 16 days ago by Andrew Beckett

1 replies • 324 views
Discussion

Cadence PEX Directory Creation - Unable to Create the Directory for Netlist

Category: Custom IC Design

By ranaya
•
updated 20 days ago by ranaya

2 replies • 370 views
Discussion

Cadence Parasitic Extraction - Location / Directory Issue

Category: Custom IC Design

By ranaya
•
updated 20 days ago by Andrew Beckett

1 replies • 272 views
Discussion

Automating Library Reference Change with Additional Parameters in New Library

Category: Custom IC Design

By AN202507174258
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started 22 days ago

0 replies • 305 views
Discussion

For a new machine, which RHEL?

Category: Custom IC Design

By kenc184
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updated 22 days ago by kenc184

3 replies • 613 views

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