Custom IC Design

Latest Posts

Discussion

How to simulate pnoise of fractional (non-integer) frequency divider

Category: Custom IC Design

By yino

$usertype
•
updated over 8 years ago by yino

2 replies • 15417 views
Discussion

ADE XL Timed Out Running Monte Carlo Simulation

Category: Custom IC Design

By spaceradlab

$usertype
•
updated over 8 years ago by Andrew Beckett

3 replies • 15283 views
Discussion

CDF instance information warning meaning

Category: Custom IC Design

By RVERP

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 14521 views
Discussion

When does opening an ADE-XL view cause also ViVa to open?

Category: Custom IC Design

By PatrikOsgnach

$usertype
•
updated over 8 years ago by PatrikOsgnach

4 replies • 14445 views
Discussion

Measurement of delay between change in value of two buses created using Analog to Digital function

Category: Custom IC Design

By prashantpd

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 15095 views
Discussion

gpdk045 vth at dcop is not same as model spec

Category: Custom IC Design

By rfham

$usertype
•
updated over 8 years ago by Andrew Beckett

2 replies • 14857 views
Discussion

how to use variable in parameter sweep

Category: Custom IC Design

By sjwprc

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 16891 views
Discussion

Monte Carlo: Define instance mismatch correlation in IC61.6/7

Category: Custom IC Design

By Majdo

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 2364 views
Discussion

multipart path - automatically fill path width with rows of subrectangles

Category: Custom IC Design

By caver456

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 682 views
Discussion

Transient Noise Simulation for Different input/output frequencies

Category: Custom IC Design

By EngrZM

$usertype
•
updated over 8 years ago by EngrZM

2 replies • 3639 views
Discussion

Copying A Maestro View and underlying schematics to a new library

Category: Custom IC Design

By Cra1g

$usertype
•
updated over 8 years ago by Cra1g

4 replies • 19106 views
Discussion

save DC operating points in ADEXL

Category: Custom IC Design

By SteveRFIC

$usertype
•
updated over 8 years ago by SteveRFIC

2 replies • 18946 views
Discussion

Variable instance number and bus width depending on CDF parameter

Category: Custom IC Design

By Johanny Saenz

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 15885 views
Discussion

PSTB loop-gain Phase-plot : error at lower frequency

Category: Custom IC Design

By jdp721

$usertype
•
updated over 8 years ago by jdp721

4 replies • 17964 views
Discussion

ADEXL: use DirectPlot->Main Form with saved data

Category: Custom IC Design

By Clidre

$usertype
•
updated over 8 years ago by Andrew Beckett

3 replies • 2089 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.