Custom IC Design

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Discussion

IO placement

Category: Custom IC Design

By Shameel

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updated over 12 years ago by Quek

1 replies • 13345 views
Discussion

layermap file

Category: Custom IC Design

By bhaskarlakshmi

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updated over 12 years ago by Quek

1 replies • 14125 views
Discussion

how to simulate delay of a wire?

Category: Custom IC Design

By rickyuexu

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updated over 12 years ago by rickyuexu

6 replies • 16073 views
Discussion

analysis

Category: Custom IC Design

By yeong

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updated over 12 years ago by Andrew Beckett

29 replies • 22746 views
Discussion

Hierarchical Parasitic Extraction & Cadence Tools

Category: Custom IC Design

By jimito13

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updated over 12 years ago by GabrielB

24 replies • 17216 views
Discussion

How do I re-load the .cadence directory via SKILL w/o restarting a session?

Category: Custom IC Design

By Julia

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updated over 12 years ago by Julia

4 replies • 1657 views
Discussion

How to write the expression for two currents' signal and plot them with Temperature

Category: Custom IC Design

By bhl3302

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updated over 12 years ago by bhl3302

2 replies • 7328 views
Discussion

problem: W and L of a transistor not shown in edit-> object-> properties

Category: Custom IC Design

By apple419

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updated over 12 years ago by beny

3 replies • 2070 views
Discussion

Histograms not showing in MC Analysis

Category: Custom IC Design

By Flyyn Rider

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updated over 12 years ago by Flyyn Rider

1 replies • 13324 views
Discussion

Regarding Smoothness in transient analysis

Category: Custom IC Design

By RFStuff

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updated over 12 years ago by Andrew Beckett

6 replies • 15725 views
Discussion

Layout pin problem: net name distributes via transistor

Category: Custom IC Design

By jeffreyprin

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started over 12 years ago

0 replies • 14016 views
Discussion

Is there a way in Verilog-A to know if transient noise analysis is run?

Category: Custom IC Design

By SharksFan

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updated over 12 years ago by Andrew Beckett

3 replies • 14785 views
Discussion

switching between spectre and mmsim

Category: Custom IC Design

By NcfC

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updated over 12 years ago by NcfC

4 replies • 15164 views
Discussion

axlExportOutputView creates an empty file

Category: Custom IC Design

By adeuser777

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updated over 12 years ago by Andrew Beckett

1 replies • 13326 views
Discussion

converting verilog to SPICE netlist

Category: Custom IC Design

By govind2306

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updated over 12 years ago by Andrew Beckett

1 replies • 20122 views

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