Custom IC Design

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Error with Assura QRC using IBM 0.13um SiGe

Category: Custom IC Design

By sriram123

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updated over 11 years ago by Andrew Beckett

1 replies • 13422 views
Discussion

Monte carlo pre-run script

Category: Custom IC Design

By LinuxMachine

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updated over 11 years ago by Andrew Beckett

1 replies • 14114 views
Discussion

Transistor Finger/Multiplier does not work

Category: Custom IC Design

By EricHsu

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updated over 11 years ago by Andrew Beckett

1 replies • 2047 views
Discussion

Capacitor Mismatch Coefficient for gpdk 180nm technology

Category: Custom IC Design

By indra0804

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updated over 11 years ago by Andrew Beckett

1 replies • 14313 views
Discussion

CMRR of an OP amp

Category: Custom IC Design

By kenambo

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updated over 11 years ago by Andrew Beckett

1 replies • 15750 views
Discussion

Veriloga Montecarlo input from spectre

Category: Custom IC Design

By jeffreyprin

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updated over 11 years ago by Andrew Beckett

1 replies • 13111 views
Discussion

Monte carlo on a verilog A custom macro model based on device instance not subckt instance

Category: Custom IC Design

By Fabb

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updated over 11 years ago by Andrew Beckett

1 replies • 14436 views
Discussion

How do I turn off flighlines from the bulk of transistors....

Category: Custom IC Design

By pham777

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updated over 11 years ago by Andrew Beckett

1 replies • 12973 views
Discussion

Component Display parameter missing in EDIT menu Cadence 6.1.6-64b

Category: Custom IC Design

By sasuke

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updated over 11 years ago by Marc Heise

1 replies • 15546 views
Discussion

Pins, Nets created are not visible

Category: Custom IC Design

By Prash123

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updated over 11 years ago by Andrew Beckett

1 replies • 13640 views
Discussion

Timestamp.....

Category: Custom IC Design

By pham777

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updated over 11 years ago by aflex

2 replies • 13189 views
Discussion

Reading a data file in Veriloga code

Category: Custom IC Design

By Sali

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updated over 11 years ago by Sali

4 replies • 17179 views
Discussion

help on using diode model in Spectre simulation

Category: Custom IC Design

By apple419

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updated over 11 years ago by Andrew Beckett

2 replies • 17221 views
Discussion

saving verilog-a triggers compilation instead of just syntax check

Category: Custom IC Design

By danmc

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updated over 11 years ago by danmc

2 replies • 13353 views
Discussion

sweep variable "bs" in hb, then use VAR("bs") in output expression, not plot in ADEXL

Category: Custom IC Design

By Taoni

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updated over 11 years ago by Andrew Beckett

6 replies • 7087 views

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