Custom IC Design

Latest Posts

Discussion

Adexl - dynamically stop transient run on event trigger

Category: Custom IC Design

By firebolt

$usertype
•
updated over 2 years ago by firebolt

11 replies • 4343 views
Discussion

portorder not being ignored?

Category: Custom IC Design

By kenc184

$usertype
•
updated over 2 years ago by kenc184

8 replies • 10350 views
Discussion

Is it possible to download the slides from online training?

Category: Custom IC Design

By delgsy

$usertype
•
updated over 2 years ago by Andrew Beckett

1 replies • 6503 views
Discussion

What does the cut pattern "farm" mean?

Category: Custom IC Design

By RVERP

$usertype
•
updated over 2 years ago by RVERP

2 replies • 1069 views
Discussion

RLC parasitic extraction type for post-layout simulation

Category: Custom IC Design

By Senan

$usertype
•
updated over 2 years ago by Senan

5 replies • 9612 views
Discussion

Digital signal overshoot and undershoot detection in Cadence

Category: Custom IC Design

By Senan

$usertype
•
updated over 2 years ago by ShawnLogan

3 replies • 8374 views
Discussion

How to acces leaf-instance of subsckt for use as probe?

Category: Custom IC Design

By jehh

$usertype
•
started over 2 years ago

0 replies • 6499 views
Discussion

Spectre parallel jobs reduce near finish

Category: Custom IC Design

By Pirate King

$usertype
•
updated over 2 years ago by Cadenceuser101

6 replies • 9303 views
Discussion

Simulating a circuit in an array

Category: Custom IC Design

By delgsy

$usertype
•
updated over 2 years ago by Andrew Beckett

3 replies • 7118 views
Discussion

Virtuoso SystemVerilog errors

Category: Custom IC Design

By HoWei

$usertype
•
updated over 2 years ago by HoWei

14 replies • 14901 views
Discussion

Multiple alignment spacing parameters

Category: Custom IC Design

By Kevin Buck

$usertype
•
updated over 2 years ago by Kevin Buck

2 replies • 7215 views
Discussion

STB Analysis: Invalid instance name

Category: Custom IC Design

By fyoh

$usertype
•
updated over 2 years ago by fyoh

6 replies • 9627 views
Discussion

ADE Results "Detailed - Transposed" and CSV export: Missing spec and testname

Category: Custom IC Design

By StephanWeber

$usertype
•
updated over 2 years ago by StephanWeber

3 replies • 1654 views
Discussion

Magnitude value in AC simulation with Cadence Virtuoso

Category: Custom IC Design

By Senan

$usertype
•
updated over 2 years ago by ShawnLogan

11 replies • 19460 views
Discussion

Convolution function of two temporal signals in Cadence Verilog-A

Category: Custom IC Design

By cheedyliew

$usertype
•
started over 2 years ago

0 replies • 6486 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.