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Custom IC Design

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  • Discussion

    Could anyone explain PSS+PAC simulation result of sampling circuit

    Category: Custom IC Design

    By fvoisin fvoisin

    •

    updated over 1 year ago by fvoisin

    2 replies • 1641 views
  • Discussion

    Pegasus DRC Run fails

    Category: Custom IC Design

    By Saumeek Saumeek

    •

    updated over 1 year ago by RobMan

    2 replies • 4409 views
  • Discussion

    ADE Schemetic simulation will not auto re-netlist Verilog-A Module

    Category: Custom IC Design

    By SimbaG SimbaG

    •

    updated over 1 year ago by Frank Wiedmann

    3 replies • 3853 views
  • Discussion

    Jitter measurement for VCO

    Category: Custom IC Design

    By TUKA TUKA

    •

    started over 1 year ago

    0 replies • 3342 views
  • Discussion

    How to add the sigma value in model card

    Category: Custom IC Design

    By CJL CJL

    •

    started over 1 year ago

    0 replies • 3228 views
  • Discussion

    Importing Spectre netlist to generate schematic

    Category: Custom IC Design

    By komal k komal k

    •

    started over 1 year ago

    0 replies • 3524 views
  • Discussion

    Change Font Size for Schematic Annotation of the DC Operating Points

    Category: Custom IC Design

    By Zol Zol

    •

    started over 1 year ago

    0 replies • 3234 views
  • Discussion

    [Continue thread] Change Virtuoso Studio ADE Windows Title Style

    Category: Custom IC Design

    By SimbaG SimbaG

    •

    updated over 1 year ago by SimbaG

    7 replies • 4698 views
  • Discussion

    *Error* eval: undefined function - mgc_calibre_run_drc

    Category: Custom IC Design

    By Saumeek Saumeek

    •

    updated over 1 year ago by Andrew Beckett

    2 replies • 1077 views
  • Discussion

    Finding the training material of the "integration innovus with virtuoso"

    Category: Custom IC Design

    By SimbaG SimbaG

    •

    updated over 1 year ago by Frank Wiedmann

    1 replies • 1101 views
  • Discussion

    PCells not found for layout in Cadence Virtuoso using GF 12nm PDK

    Category: Custom IC Design

    By Saumeek Saumeek

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 4086 views
  • Discussion

    expand combined libraries to tree view on start in LibraryManager

    Category: Custom IC Design

    By cato cato

    •

    updated over 1 year ago by cato

    2 replies • 3462 views
  • Discussion

    Why the electromagnetic solver not found?

    Category: Custom IC Design

    By Restart Restart

    •

    updated over 1 year ago by Restart

    1 replies • 3427 views
  • Discussion

    Mixer Stability

    Category: Custom IC Design

    By TobyK TobyK

    •

    started over 1 year ago

    0 replies • 3231 views
  • Discussion

    How to set the stress conditions in a reliability analysis in ADE explorer?

    Category: Custom IC Design

    By unSkilled unSkilled

    •

    updated over 1 year ago by JankoK

    1 replies • 3863 views
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