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Custom IC Design

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    Finding and transferring the value of a variable that gives the minimum value of an output in a test where more than one variable swept to another test using calcVal function in Assembler

    Category: Custom IC Design

    By baltaci

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    updated over 2 years ago by ShawnLogan

    8 replies • 10351 views
  • Discussion

    Efficient labeling method?

    Category: Custom IC Design

    By lightcoming

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    updated over 2 years ago by Andrew Beckett

    1 replies • 9080 views
  • Discussion

    How to make sure Pnoise is giving correct results?

    Category: Custom IC Design

    By HnArd

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    updated over 2 years ago by ShawnLogan

    3 replies • 8244 views
  • Discussion

    Cannot Create an auto pin

    Category: Custom IC Design

    By nienjt

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    started over 2 years ago

    0 replies • 6627 views
  • Discussion

    Parasitic capacitance of the drain of abutted transistors apparently counted twice in post-layout simulation

    Category: Custom IC Design

    By massbarb

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    updated over 2 years ago by massbarb

    3 replies • 8826 views
  • Discussion

    How To Add Arguments to systemVerilog Extraction

    Category: Custom IC Design

    By YB36

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    started over 2 years ago

    0 replies • 7553 views
  • Discussion

    Reliability Analysis Tutorial

    Category: Custom IC Design

    By illaoi

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    •

    updated over 2 years ago by ShawnLogan

    1 replies • 8842 views
  • Discussion

    Using 'temperature' as a design variable breaks calcVal functionality

    Category: Custom IC Design

    By Kevin Buck

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    updated over 2 years ago by Kevin Buck

    1 replies • 1830 views
  • Discussion

    FET Noise in BSIM4

    Category: Custom IC Design

    By illaoi

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    updated over 2 years ago by ShawnLogan

    4 replies • 9293 views
  • Discussion

    Unable to change reference of library from cdsDefTechLib to actual pdk

    Category: Custom IC Design

    By sidm

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    updated over 2 years ago by Andrew Beckett

    3 replies • 9165 views
  • Discussion

    common mode level in vcvs

    Category: Custom IC Design

    By paulinho

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    updated over 2 years ago by Andrew Beckett

    2 replies • 10745 views
  • Discussion

    VerilogA - command: $root

    Category: Custom IC Design

    By rrihak

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    updated over 2 years ago by MarcelAhmedzai

    1 replies • 1103 views
  • Discussion

    Measuring across corners or parameters, then equation using results

    Category: Custom IC Design

    By TempViator

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    updated over 2 years ago by amac

    1 replies • 8408 views
  • Discussion

    Whether virtuoso only loads the first .cdsinit file it finds

    Category: Custom IC Design

    By lightyear

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    updated over 2 years ago by lightyear

    2 replies • 8618 views
  • Discussion

    Differce between IC5 & IC6 in pnoise simulation(jitter)

    Category: Custom IC Design

    By HsiuMin

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    •

    updated over 2 years ago by ShawnLogan

    1 replies • 1272 views
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