Custom IC Design

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Checking installation of PDK is correct

Category: Custom IC Design

By CxD7

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updated over 7 years ago by CxD7

2 replies • 16786 views
Discussion

CDF parameters reusing default value from veriloga

Category: Custom IC Design

By ernie123

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updated over 7 years ago by ernie123

2 replies • 14665 views
Discussion

APS: better Hyperthreading ON or OFF on the machine?

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

4 replies • 15723 views
Discussion

Library Manager: .cdsenv / .cdsinit settings not taking effect

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

4 replies • 24566 views
Discussion

design kits for a new member in cadence

Category: Custom IC Design

By tashtoush

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updated over 7 years ago by tashtoush

6 replies • 16125 views
Discussion

fail to use VAR as 'tran' analysis parameter

Category: Custom IC Design

By fatcat1206

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updated over 7 years ago by Andrew Beckett

3 replies • 4032 views
Discussion

How do you generate a layout from schematic in Virtuoso IC 6.1.5?

Category: Custom IC Design

By ernie123

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updated over 7 years ago by Andrew Beckett

3 replies • 19340 views
Discussion

how to enable to show all the simulation warnings

Category: Custom IC Design

By enzhu

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updated over 7 years ago by Andrew Beckett

1 replies • 15060 views
Discussion

Plotting across corners with internal sweep in maestro

Category: Custom IC Design

By Gabriel Puech

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updated over 7 years ago by Andrew Beckett

7 replies • 17790 views
Discussion

Custom digital placer can't use tap-cell

Category: Custom IC Design

By jsundermeyer

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updated over 7 years ago by Andrew Beckett

5 replies • 2014 views
Discussion

Export data to CSV format

Category: Custom IC Design

By CPete

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updated over 7 years ago by Andrew Beckett

21 replies • 57855 views
Discussion

ADE-XL: force re-evaluation of Matlab script edited outside Virtuoso

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

2 replies • 13946 views
Discussion

VPS-L: vsaplot can't find "design.info" file

Category: Custom IC Design

By KurtKimber1

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started over 7 years ago

0 replies • 411 views
Discussion

Strange problem when working with small currents in ADE L

Category: Custom IC Design

By dpalomeq

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updated over 7 years ago by dpalomeq

4 replies • 14807 views
Discussion

set parameter in definition files of adexl but given error of variable not defined (monte carlo simulation)

Category: Custom IC Design

By monglebest

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updated over 7 years ago by Andrew Beckett

5 replies • 17406 views

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