Custom IC Design

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Term Order setup for spice reference files

Category: Custom IC Design

By AncisMichele

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updated over 3 years ago by AncisMichele

2 replies • 10720 views
Discussion

Two step trimming in Maestro Assembler. Difficulty encountered trying to calculate the trimming code in the second trimming step.

Category: Custom IC Design

By IceTea

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updated over 3 years ago by IceTea

5 replies • 11626 views
Discussion

VerilogA $fopen issues when used in a loop

Category: Custom IC Design

By AAbdelRahman

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updated over 3 years ago by AAbdelRahman

6 replies • 12887 views
Discussion

Saving Assistants' location in Schematic Editor

Category: Custom IC Design

By AncisMichele

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updated over 3 years ago by AncisMichele

2 replies • 1199 views
Discussion

Seal-Ring DRC errors

Category: Custom IC Design

By Senan

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started over 3 years ago

0 replies • 10510 views
Discussion

Locating a result value from montecarlo run table in Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

2 replies • 9783 views
Discussion

Dynamic paramters "temp" doesn't work? (Solver = Ultrasim, transient analysis)

Category: Custom IC Design

By SpiceMonkey

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updated over 3 years ago by Andrew Beckett

3 replies • 2371 views
Discussion

analog digital output average mean value

Category: Custom IC Design

By abdurrahman0234

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updated over 3 years ago by FormerMember

21 replies • 18688 views
Discussion

VerilogA loop generate constructs not defining multiple sub modules

Category: Custom IC Design

By AAbdelRahman

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updated over 3 years ago by AAbdelRahman

8 replies • 13609 views
Discussion

How to measure node to node capacitance?

Category: Custom IC Design

By Holz

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updated over 3 years ago by FormerMember

3 replies • 13117 views
Discussion

variables from CDF parameters

Category: Custom IC Design

By amacSS

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updated over 3 years ago by Andrew Beckett

5 replies • 12605 views
Discussion

Set ignoredesigchangesduringrun locally / per session / per maestro cell

Category: Custom IC Design

By jehh

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updated over 3 years ago by Andrew Beckett

4 replies • 10481 views
Discussion

DRC Cadence

Category: Custom IC Design

By Zahir Kaka

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updated over 3 years ago by Andrew Beckett

1 replies • 9165 views
Discussion

ERROR (ASSEMBLER-5011) and high memory usage after some long simulations

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 9523 views
Discussion

Coplanar wavewguide with GND plane

Category: Custom IC Design

By BoniUNIPR

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updated over 3 years ago by BoniUNIPR

2 replies • 9630 views

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