Custom IC Design

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Discussion

Using extracted view with iterated instance

Category: Custom IC Design

By Mathieu Chene

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updated over 1 year ago by Mathieu Chene

2 replies • 5107 views
Discussion

Creating vector variable in ADE XL to configure Verilog-A module

Category: Custom IC Design

By RaffaeleUdS

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updated over 1 year ago by Andrew Beckett

1 replies • 4819 views
Discussion

Any way to set a default value for the design variables in ADE explorer

Category: Custom IC Design

By jason1127

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updated over 1 year ago by Andrew Beckett

1 replies • 4817 views
Discussion

Previously closed windows minimize upon reopening in IC23.10

Category: Custom IC Design

By LMendolia

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updated over 1 year ago by Andrew Beckett

1 replies • 4891 views
Discussion

How to repair miscalculated bBox of an object that I cannot spot on the layout?

Category: Custom IC Design

By MichalWolodzko

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updated over 1 year ago by MichalWolodzko

2 replies • 4887 views
Discussion

Simulation temerature dependent on DC power

Category: Custom IC Design

By Martinsh

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updated over 1 year ago by ShawnLogan

7 replies • 5907 views
Discussion

Cadence Layout DRC Pins Error

Category: Custom IC Design

By Sarah1898

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updated over 1 year ago by ShawnLogan

4 replies • 6884 views
Discussion

Align hierarchic pins in layout with SKILL script.

Category: Custom IC Design

By MichalWolodzko

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started over 1 year ago

0 replies • 4481 views
Discussion

scaling and DBU/UU - XStream vs XOasis

Category: Custom IC Design

By vshih

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updated over 1 year ago by Andrew Beckett

1 replies • 1326 views
Discussion

How to setup monte-carlo run for variation analysis in virtuoso

Category: Custom IC Design

By supriyo1985

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updated over 1 year ago by Andrew Beckett

1 replies • 5106 views
Discussion

XNOR Gate Operation Issue in Cadence

Category: Custom IC Design

By Maria98

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updated over 1 year ago by Maria98

2 replies • 5610 views
Discussion

Format/Syntax for Writing Aged Model Files for Reliability Simulations

Category: Custom IC Design

By rahulsingh

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updated over 1 year ago by rahulsingh

6 replies • 2629 views
Discussion

[Solved] Cannot Direct Plot PAC Current (Even though it is saved in outputs!)

Category: Custom IC Design

By MahdiMohammadi

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updated over 1 year ago by MahdiMohammadi

2 replies • 5667 views
Discussion

How to pop-up Log file of ADEXL/ADE Explorer once simulation

Category: Custom IC Design

By Binhngo1210

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updated over 1 year ago by Binhngo1210

3 replies • 2399 views
Discussion

using different specs for Fresh and playback at the verifier

Category: Custom IC Design

By analog2

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updated over 1 year ago by Andrew Beckett

1 replies • 4820 views

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