Custom IC Design

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Discussion

Unable to plot from ADE Assembler results tab

Category: Custom IC Design

By unSkilled

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updated over 4 years ago by Andrew Beckett

3 replies • 13091 views
Discussion

Edit schematic with python

Category: Custom IC Design

By darylpan

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updated over 4 years ago by Andrew Beckett

1 replies • 12976 views
Discussion

APS++ for AMS mode (NOT in spectre mode)

Category: Custom IC Design

By RFStuff

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updated over 4 years ago by RFStuff

2 replies • 10837 views
Discussion

Model parameters clarity

Category: Custom IC Design

By shashwatss

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updated over 4 years ago by Andrew Beckett

1 replies • 12022 views
Discussion

How can I solve the "ERROR (VIVA-9000)" ?

Category: Custom IC Design

By ichiro

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updated over 4 years ago by ichiro

6 replies • 5147 views
Discussion

parasitic extraction on "updated" schematics

Category: Custom IC Design

By life

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updated over 4 years ago by FormerMember

1 replies • 1207 views
Discussion

Any bindkey to run "netlist -> recreate"?

Category: Custom IC Design

By sjwprcker

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updated over 4 years ago by sjwprcker

4 replies • 1497 views
Discussion

Suppress: *WARNING* COMBINE attribute library not defined

Category: Custom IC Design

By Aldo2

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updated over 4 years ago by Andrew Beckett

18 replies • 23540 views
Discussion

ADE Explorer - Spec Pass/Fail

Category: Custom IC Design

By life

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updated over 4 years ago by life

1 replies • 2288 views
Discussion

Update W/L number in instance property, but resistor "r "value isn't change accordingly

Category: Custom IC Design

By ringamp

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updated over 4 years ago by ringamp

2 replies • 2228 views
Discussion

Can I use a variable as interpolation point in the value function?

Category: Custom IC Design

By maaz2020

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updated over 4 years ago by maaz2020

5 replies • 14262 views
Discussion

Verilog-AMS Simulation speed issue while using $table_model for reading from a file.

Category: Custom IC Design

By RFStuff

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updated over 4 years ago by Andrew Beckett

1 replies • 10672 views
Discussion

How to pass a real array as an input argument to a function in Verilog (in AMS simulation)

Category: Custom IC Design

By RFStuff

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updated over 4 years ago by RFStuff

2 replies • 11978 views
Discussion

Restrict ICPR SGE Job to only run 1 simulation point (ADE Assembler)

Category: Custom IC Design

By jehh

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updated over 4 years ago by Andrew Beckett

1 replies • 11706 views
Discussion

How can I fix the error in my simulation?

Category: Custom IC Design

By yysunj

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updated over 4 years ago by Andrew Beckett

3 replies • 12212 views

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