Custom IC Design

Latest Posts

Discussion

[ADE XL] Compiling verilog-A module

Category: Custom IC Design

By Seokhyun Jeong

$usertype
•
started over 8 years ago

0 replies • 13796 views
Discussion

Layout XL: how to set default options for Selection Protection?

Category: Custom IC Design

By dontpanic

$usertype
•
updated over 8 years ago by dontpanic

4 replies • 15931 views
Discussion

How to subtract a wire/path from a polygon

Category: Custom IC Design

By JWHoll

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 3709 views
Discussion

QRC (EXT91) always fails

Category: Custom IC Design

By Zach

$usertype
•
updated over 8 years ago by Quek

6 replies • 16741 views
Discussion

How to store a value/Store function in Verilog-A/AMS

Category: Custom IC Design

By Hasan91

$usertype
•
updated over 8 years ago by Hasan91

2 replies • 2085 views
Discussion

IQ cross-talk: simulation artefact?

Category: Custom IC Design

By itos

$usertype
•
updated over 8 years ago by itos

4 replies • 15253 views
Discussion

Error while simulating verilog-A block

Category: Custom IC Design

By tangudubharat

$usertype
•
updated over 8 years ago by tangudubharat

6 replies • 17034 views
Discussion

Sampled point inaccuracy in AMS simulation

Category: Custom IC Design

By auran

$usertype
•
updated over 8 years ago by auran

4 replies • 15636 views
Discussion

VHDL-AMS library issue?

Category: Custom IC Design

By srana01

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 14828 views
Discussion

ADE-XL doesn't pick up readic initial condition file/ How to properly pass initial condition setup into ADEXL?

Category: Custom IC Design

By RFAnalog123

$usertype
•
updated over 8 years ago by Andrew Beckett

2 replies • 3391 views
Discussion

Virtuoso Spice In grouping instances

Category: Custom IC Design

By shredds

$usertype
•
updated over 8 years ago by shredds

2 replies • 13724 views
Discussion

dcOp sweep

Category: Custom IC Design

By drdanmc

$usertype
•
updated over 8 years ago by Andrew Beckett

3 replies • 17078 views
Discussion

Extract single net from layout

Category: Custom IC Design

By drdanmc

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 14506 views
Discussion

vsin frequency precision, and tips for coherent sampling

Category: Custom IC Design

By msharma

$usertype
•
updated over 8 years ago by msharma

2 replies • 15045 views
Discussion

phase noise sim for driven circuit with non-ideal input

Category: Custom IC Design

By SteveRFIC

$usertype
•
started over 8 years ago

0 replies • 13955 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.