Custom IC Design

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save option not working for ac within transient

Category: Custom IC Design

By Steve Mikes

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updated over 12 years ago by Andrew Beckett

5 replies • 14971 views
Discussion

ADEXL: backannotation of transient operating points for montecarlo points

Category: Custom IC Design

By spectrallypure

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updated over 12 years ago by spectrallypure

3 replies • 15029 views
Discussion

Why the l(m) and w(m) are always set 5e-06m in model parameter field after any simulation?

Category: Custom IC Design

By Alex Liao

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updated over 12 years ago by Alex Liao

2 replies • 767 views
Discussion

Transien response of inverter

Category: Custom IC Design

By sreeni

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updated over 12 years ago by sreeni

2 replies • 13678 views
Discussion

Cadence IC 5.1 Libmanager problem

Category: Custom IC Design

By Darshak

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updated over 12 years ago by Darshak

2 replies • 14049 views
Discussion

Switch Extracted view names in ADEXL

Category: Custom IC Design

By ank0888

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updated over 12 years ago by ank0888

3 replies • 16817 views
Discussion

Error while plotting Extracted simulation results

Category: Custom IC Design

By aravindvj

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updated over 12 years ago by Andrew Beckett

7 replies • 21247 views
Discussion

ADEXL Montecarlo, only netlisting

Category: Custom IC Design

By demsar

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updated over 12 years ago by Andrew Beckett

6 replies • 16626 views
Discussion

Error in Simulating Verilog XL+Analog in spectreVerilog

Category: Custom IC Design

By ksnf3000

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updated over 12 years ago by Andrew Beckett

2 replies • 2226 views
Discussion

How to set the model parameter STIMOD in simulation?

Category: Custom IC Design

By Alex Liao

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updated over 12 years ago by Alex Liao

11 replies • 21127 views
Discussion

ADE/ViVA Toggle Trace Visibility Bindkey

Category: Custom IC Design

By mconte

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updated over 12 years ago by mconte

2 replies • 1494 views
Discussion

how to list all devices and their operating region in a file

Category: Custom IC Design

By kxlux

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updated over 12 years ago by Andrew Beckett

1 replies • 14719 views
Discussion

Error in verilogA

Category: Custom IC Design

By sreeni

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updated over 12 years ago by sreeni

4 replies • 16305 views
Discussion

Cadence ADEXL: how to merge troubleshot point with rest of montecarlo data

Category: Custom IC Design

By spectrallypure

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updated over 12 years ago by Frank Wiedmann

12 replies • 20055 views
Discussion

skill to plot waveform contained in a file into w-viewer (could be VIVA)

Category: Custom IC Design

By azde

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updated over 12 years ago by Andrew Beckett

3 replies • 14262 views

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