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Custom IC Design

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  • Discussion

    Could not find netlist procedure:SpectreFNPairs instance

    Category: Custom IC Design

    By ranaya ranaya

    •

    updated 9 days ago by Andrew Beckett

    5 replies • 742 views
  • Discussion

    LUT implementation using VerilogA code In Cadence Virtuoso

    Category: Custom IC Design

    By ZulfiqarKiani ZulfiqarKiani

    •

    started 10 days ago

    0 replies • 384 views
  • Discussion

    Sorting variables by name alphanumerically in Virtuoso ADE Assembler / maestro

    Category: Custom IC Design

    By Dominique8765 Dominique8765

    •

    updated 10 days ago by Andrew Beckett

    1 replies • 211 views
  • Discussion

    sweeping transistor number of fingers in a simulation

    Category: Custom IC Design

    By TommasoF TommasoF

    •

    updated 11 days ago by TommasoF

    2 replies • 682 views
  • Discussion

    xrun: *F,SROOTE: Cannot find the Spectre installation

    Category: Custom IC Design

    By Leo 93 Leo 93

    •

    updated 12 days ago by Andrew Beckett

    3 replies • 461 views
  • Discussion

    use DC sweep variable to set another variable

    Category: Custom IC Design

    By Darrell L Darrell L

    •

    updated 12 days ago by Darrell L

    2 replies • 453 views
  • Discussion

    automate cadence design to avoid time consuming steps for simulation using python subprocess module.

    Category: Custom IC Design

    By AP202507218251 AP202507218251

    •

    started 13 days ago

    0 replies • 213 views
  • Discussion

    ERROR (NVN-13010): Cell rupolym is not defined while running Pegasus LVS

    Category: Custom IC Design

    By yogeshjaiswalCAD yogeshjaiswalCAD

    •

    updated 13 days ago by Andrew Beckett

    3 replies • 377 views
  • Discussion

    All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

    Category: Custom IC Design

    By DavidGogiber DavidGogiber

    •

    updated 14 days ago by Andrew Beckett

    4 replies • 712 views
  • Discussion

    Cannot Copy Variable to Other Tests

    Category: Custom IC Design

    By MM202507017815 MM202507017815

    •

    updated 16 days ago by Andrew Beckett

    1 replies • 319 views
  • Discussion

    Cadence PEX Directory Creation - Unable to Create the Directory for Netlist

    Category: Custom IC Design

    By ranaya ranaya

    •

    updated 19 days ago by ranaya

    2 replies • 366 views
  • Discussion

    Cadence Parasitic Extraction - Location / Directory Issue

    Category: Custom IC Design

    By ranaya ranaya

    •

    updated 19 days ago by Andrew Beckett

    1 replies • 270 views
  • Discussion

    Automating Library Reference Change with Additional Parameters in New Library

    Category: Custom IC Design

    By AN202507174258 AN202507174258

    •

    started 21 days ago

    0 replies • 302 views
  • Discussion

    For a new machine, which RHEL?

    Category: Custom IC Design

    By kenc184 kenc184

    •

    updated 22 days ago by kenc184

    3 replies • 609 views
  • Discussion

    Parameterization of transistor model BSIM4 parameters

    Category: Custom IC Design

    By Sourav Chakraborty Sourav Chakraborty

    •

    started 22 days ago

    0 replies • 327 views
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