Custom IC Design

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Discussion

Saving the results of the Monte Carlo simulation with the Spectre Netlist scripting

Category: Custom IC Design

By Jafar Shamsi

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updated over 4 years ago by Jafar Shamsi

5 replies • 13133 views
Discussion

Displaying value in ADE Explorer Outputs without generating a plot

Category: Custom IC Design

By mikewu

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updated over 4 years ago by mikewu

3 replies • 14506 views
Discussion

How to save inherited pin current in ADE Assembler using AMS simulator

Category: Custom IC Design

By LukeAndrew

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started over 4 years ago

0 replies • 11477 views
Discussion

Delay and bandwidth calculation for analog signals in Cadence

Category: Custom IC Design

By Farnaz

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updated over 4 years ago by Farnaz

2 replies • 13104 views
Discussion

Using a filter model of arbitrary poles and zeros in ADE

Category: Custom IC Design

By RFStuff

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updated over 4 years ago by Andrew Beckett

1 replies • 12373 views
Discussion

Voltus-Fi PDB File Location

Category: Custom IC Design

By phill1127

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started over 4 years ago

0 replies • 11015 views
Discussion

Continuing a sim from a previous instant

Category: Custom IC Design

By mnagaraj

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updated over 4 years ago by Andrew Beckett

1 replies • 10509 views
Discussion

Partial LVS check

Category: Custom IC Design

By Senan

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updated over 4 years ago by Senan

2 replies • 11449 views
Discussion

How can I import the model card to the Cadence?

Category: Custom IC Design

By yysunj

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updated over 4 years ago by yysunj

8 replies • 15202 views
Discussion

Need help with Cadence Virtuoso pop-ups display

Category: Custom IC Design

By Phong Phan

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updated over 4 years ago by Phong Phan

2 replies • 12044 views
Discussion

Is there a way to name matrixial instances or nets?

Category: Custom IC Design

By Johanny Saenz

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updated over 4 years ago by Andrew Beckett

1 replies • 10563 views
Discussion

Need to get routing layers info from tech db

Category: Custom IC Design

By Utkarsh03

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updated over 4 years ago by Utkarsh03

4 replies • 12324 views
Discussion

Monte carlo simulation error (no process variations were specified in the statistics block)

Category: Custom IC Design

By Afshin Amoo

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updated over 4 years ago by Afshin Amoo

2 replies • 15046 views
Discussion

oppoint using verilog a

Category: Custom IC Design

By Yea Chul

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updated over 4 years ago by Andrew Beckett

2 replies • 12005 views
Discussion

plotting loop gain in ADE Assembler

Category: Custom IC Design

By robert 21

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updated over 4 years ago by Andrew Beckett

4 replies • 14076 views

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