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Custom IC Design

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  • Discussion

    how to set a bindkey to display multiple layers ?

    Category: Custom IC Design

    By Nhumai

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    updated over 7 years ago by Andrew Beckett

    8 replies • 20625 views
  • Discussion

    Monte Carlo for Verilog A based model file

    Category: Custom IC Design

    By Shobhitkareer

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    •

    updated over 7 years ago by Shobhitkareer

    2 replies • 14609 views
  • Discussion

    Preventing a stupid schematic mistake with NMOS back-gates

    Category: Custom IC Design

    By CADcasualty

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    •

    updated over 7 years ago by CADcasualty

    3 replies • 16229 views
  • Discussion

    Create a symbol from layout

    Category: Custom IC Design

    By Sinochka

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    •

    updated over 7 years ago by Sinochka

    13 replies • 26594 views
  • Discussion

    Include CDF callback parameters in netlist

    Category: Custom IC Design

    By Jan Cools

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    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 14679 views
  • Discussion

    Assura selected rule checking

    Category: Custom IC Design

    By VaibhavAR

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    updated over 7 years ago by Quek

    4 replies • 14123 views
  • Discussion

    CDL import with SpiceIn: W + L wrong!

    Category: Custom IC Design

    By bdjones1

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    •

    updated over 7 years ago by Andrew Beckett

    4 replies • 19980 views
  • Discussion

    Verilog A to symbol

    Category: Custom IC Design

    By Shobhitkareer

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    •

    updated over 7 years ago by Andrew Beckett

    19 replies • 25163 views
  • Discussion

    Multiple flight wires to symbol terminal

    Category: Custom IC Design

    By alecadair

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    •

    updated over 7 years ago by Andrew Beckett

    3 replies • 15212 views
  • Discussion

    Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in verilog A when they are used in 'if -else statement'

    Category: Custom IC Design

    By KiranTej

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    updated over 7 years ago by Andrew Beckett

    11 replies • 8916 views
  • Discussion

    ADE XL new test addition on a running simulation

    Category: Custom IC Design

    By VEVAD

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    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 13008 views
  • Discussion

    How to use rand_bit_stream for trasimpedance amplifier ?

    Category: Custom IC Design

    By salar1991

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    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 13793 views
  • Discussion

    Virtuoso L and virtuoso xl cost ?

    Category: Custom IC Design

    By Marben

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    •

    updated over 7 years ago by Marben

    2 replies • 16914 views
  • Discussion

    problem with resistor in corner analysis

    Category: Custom IC Design

    By salar1991

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    •

    updated over 7 years ago by salar1991

    2 replies • 14328 views
  • Discussion

    ade explorer set instance value

    Category: Custom IC Design

    By rfham

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    •

    updated over 7 years ago by Andrew Beckett

    5 replies • 15171 views
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