Custom IC Design

Latest Posts

Discussion

Remove update text on schematic?

Category: Custom IC Design

By kenc184

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updated over 1 year ago by Andrew Beckett

4 replies • 6063 views
Discussion

ADE Explorer Design Variables sweep sets

Category: Custom IC Design

By nfathy

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updated over 1 year ago by nfathy

3 replies • 8376 views
Discussion

Post-layout simulation without spectre view in transistor cell

Category: Custom IC Design

By Javadgo

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updated over 1 year ago by Javadgo

6 replies • 7578 views
Discussion

ADE including a simulation file with a relative path

Category: Custom IC Design

By Huf

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started over 1 year ago

0 replies • 5288 views
Discussion

ADE (Explorer / Assembler) Stimuli Assignment as a floating voltage source

Category: Custom IC Design

By Huf

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started over 1 year ago

0 replies • 4979 views
Discussion

Can't unlock explorer run on ADE Assembler

Category: Custom IC Design

By Thais

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updated over 1 year ago by Andrew Beckett

1 replies • 1650 views
Discussion

Is it possible to setup Layout GXL to use multiple CPU cores?

Category: Custom IC Design

By RuihW

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started over 2 years ago

0 replies • 5041 views
Discussion

VPULSE PARAMETERS INDICATION ??

Category: Custom IC Design

By ganesh9989

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updated over 2 years ago by Andrew Beckett

1 replies • 5968 views
Discussion

Change setup of the extracted netlist (Calibre view) -- extraction with QRC

Category: Custom IC Design

By BitanMallik

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started over 2 years ago

0 replies • 807 views
Discussion

LEF generated with non-used layer info

Category: Custom IC Design

By RuihW

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started over 2 years ago

0 replies • 5254 views
Discussion

Assembler Global Optimization

Category: Custom IC Design

By sram17

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updated over 2 years ago by sram17

1 replies • 5460 views
Discussion

Device Check Asserts that only apply within a specific time window

Category: Custom IC Design

By dconnern33

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started over 2 years ago

0 replies • 5584 views
Discussion

input-referred noise measurement issue

Category: Custom IC Design

By engmsalik321

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updated over 2 years ago by Andrew Beckett

4 replies • 9005 views
Discussion

ASU 7nm installation in Cadence Virtuoso

Category: Custom IC Design

By samanway

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updated over 2 years ago by Andrew Beckett

1 replies • 5691 views
Discussion

how to write log while using features of Advanced Optimization ?

Category: Custom IC Design

By Monarch03116

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updated over 2 years ago by Andrew Beckett

1 replies • 5156 views

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