Custom IC Design

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Discussion

portorder not being ignored?

Category: Custom IC Design

By kenc184

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updated over 2 years ago by kenc184

8 replies • 10339 views
Discussion

Is it possible to download the slides from online training?

Category: Custom IC Design

By delgsy

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updated over 2 years ago by Andrew Beckett

1 replies • 6495 views
Discussion

What does the cut pattern "farm" mean?

Category: Custom IC Design

By RVERP

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updated over 2 years ago by RVERP

2 replies • 1069 views
Discussion

RLC parasitic extraction type for post-layout simulation

Category: Custom IC Design

By Senan

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updated over 2 years ago by Senan

5 replies • 9591 views
Discussion

Digital signal overshoot and undershoot detection in Cadence

Category: Custom IC Design

By Senan

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updated over 2 years ago by ShawnLogan

3 replies • 8360 views
Discussion

How to acces leaf-instance of subsckt for use as probe?

Category: Custom IC Design

By jehh

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started over 2 years ago

0 replies • 6490 views
Discussion

Spectre parallel jobs reduce near finish

Category: Custom IC Design

By Pirate King

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updated over 2 years ago by Cadenceuser101

6 replies • 9293 views
Discussion

Simulating a circuit in an array

Category: Custom IC Design

By delgsy

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updated over 2 years ago by Andrew Beckett

3 replies • 7110 views
Discussion

Virtuoso SystemVerilog errors

Category: Custom IC Design

By HoWei

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updated over 2 years ago by HoWei

14 replies • 14882 views
Discussion

Multiple alignment spacing parameters

Category: Custom IC Design

By Kevin Buck

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updated over 2 years ago by Kevin Buck

2 replies • 7207 views
Discussion

STB Analysis: Invalid instance name

Category: Custom IC Design

By fyoh

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updated over 2 years ago by fyoh

6 replies • 9616 views
Discussion

ADE Results "Detailed - Transposed" and CSV export: Missing spec and testname

Category: Custom IC Design

By StephanWeber

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updated over 2 years ago by StephanWeber

3 replies • 1652 views
Discussion

Magnitude value in AC simulation with Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 2 years ago by ShawnLogan

11 replies • 19429 views
Discussion

Convolution function of two temporal signals in Cadence Verilog-A

Category: Custom IC Design

By cheedyliew

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started over 2 years ago

0 replies • 6478 views
Discussion

Design and placement of hard macros

Category: Custom IC Design

By toufiqhanik

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started over 2 years ago

0 replies • 6797 views

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