Custom IC Design

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Last Time Value of a Tran-Simulation as Final Value in integ-Function in VIVA-Calculator

Category: Custom IC Design

By iq79

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updated over 3 years ago by iq79

6 replies • 9392 views
Discussion

Importing psf file from a old mastero run to an existing mastero for the same testbench schematic

Category: Custom IC Design

By hdeshmukhnvidia

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updated over 3 years ago by Andrew Beckett

5 replies • 8633 views
Discussion

how to input hex to a 32bit bus pin

Category: Custom IC Design

By Karev11

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updated over 3 years ago by Andrew Beckett

1 replies • 8143 views
Discussion

setting temperature by veriloga via cds_set_temperature and make it work for stb analysis

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by drdanmc

4 replies • 10987 views
Discussion

Transmission Line Simulation in EMX

Category: Custom IC Design

By Sumit Dash

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updated over 3 years ago by drdanmc

1 replies • 11027 views
Discussion

pss pac: sideband transfer function accuracy vs. maxacfrequency

Category: Custom IC Design

By ashwinrs

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updated over 3 years ago by Andrew Beckett

1 replies • 8633 views
Discussion

Spectre segmentation fault

Category: Custom IC Design

By Pavel2022

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updated over 3 years ago by Andrew Beckett

1 replies • 14931 views
Discussion

How to get rid of Weight column for Results tab in ADE?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by Andrew Beckett

5 replies • 9453 views
Discussion

Can we disable some values in the corner setup temporarily?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by StephanWeber

2 replies • 7985 views
Discussion

Noise analysis

Category: Custom IC Design

By shaarawy2023

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updated over 3 years ago by Andrew Beckett

1 replies • 7371 views
Discussion

In the Assembler corner UI: Can we make one corner variable dependent on another variable?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by FormerMember

3 replies • 8289 views
Discussion

Problem with calibre RVE Highlights

Category: Custom IC Design

By RicardoGV1

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updated over 3 years ago by RicardoGV1

5 replies • 12020 views
Discussion

Cadence liberate: Different vdd value for backgate

Category: Custom IC Design

By NKFET

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started over 3 years ago

0 replies • 7162 views
Discussion

Can I preset the width and length of simulator log file viewer?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by StephanWeber

5 replies • 8532 views
Discussion

python code to compare 2 LEF

Category: Custom IC Design

By san2696

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updated over 3 years ago by san2696

2 replies • 8342 views

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