Custom IC Design

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ADEXL - Using initial conditions from a first sim in a second sim

Category: Custom IC Design

By cdonovan

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updated over 9 years ago by cdonovan

4 replies • 3781 views
Discussion

How do I save/sweep dc operating points via Jazz?

Category: Custom IC Design

By KH28

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updated over 9 years ago by Andrew Beckett

1 replies • 1016 views
Discussion

How to streamout a gds and will have an output that is flattened

Category: Custom IC Design

By jorenrefuerzo

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updated over 9 years ago by Andrew Beckett

9 replies • 21222 views
Discussion

layout XL - flag drawing touching blockage?

Category: Custom IC Design

By yeh1

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updated over 9 years ago by Andrew Beckett

1 replies • 793 views
Discussion

Using ALTER statement in ADEL/XL

Category: Custom IC Design

By AlbertoGS

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updated over 9 years ago by Andrew Beckett

6 replies • 3539 views
Discussion

Specifying verilog plusargs when recomputing hierarchy in the Virtuoso Hierarchy Editor

Category: Custom IC Design

By chiraagjuvekar

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updated over 9 years ago by Andrew Beckett

1 replies • 13430 views
Discussion

Returning multiple variables in SKILL function

Category: Custom IC Design

By RFStuff

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updated over 9 years ago by Andrew Beckett

11 replies • 19565 views
Discussion

bindkey function with wheel button

Category: Custom IC Design

By SteveRFIC

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updated over 9 years ago by Andrew Beckett

4 replies • 14618 views
Discussion

Text view in read-only mode

Category: Custom IC Design

By Eric L14

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updated over 9 years ago by Andrew Beckett

7 replies • 17101 views
Discussion

Sampling a waveform at non-periodic times using Calculator functions

Category: Custom IC Design

By gvita

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updated over 9 years ago by Frank Wiedmann

1 replies • 15118 views
Discussion

spectre input.cs : conditional equation in .measure (min of 2 measurements)

Category: Custom IC Design

By samung

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updated over 9 years ago by samung

2 replies • 13525 views
Discussion

Identical reference and compared psf to amsDmv

Category: Custom IC Design

By FormerMember

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updated over 9 years ago by FormerMember

2 replies • 3561 views
Discussion

Cadence environment setup: Cadence 6.1.5 is suddenly stopped

Category: Custom IC Design

By Duy Hien

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updated over 9 years ago by Duy Hien

2 replies • 16077 views
Discussion

Liberate: Characterize standard cell with feedback path (no FF, no Latch)

Category: Custom IC Design

By marten

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started over 9 years ago

0 replies • 13345 views
Discussion

Error found by spectre during hierarchy flattening.ERROR(CMI-2116): I91: Too few terminals given(4<6).

Category: Custom IC Design

By yeatsss

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updated over 9 years ago by yeatsss

1 replies • 4874 views

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