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Custom IC Design

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  • Discussion

    Abstract Generator : tech file and origin in LEF file

    Category: Custom IC Design

    By samung

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    updated over 11 years ago by samung

    2 replies • 15885 views
  • Discussion

    Pin definition in layout.oa (layer, connectivity) ?

    Category: Custom IC Design

    By samung

    $usertype

    •

    updated over 11 years ago by samung

    2 replies • 16078 views
  • Discussion

    Delay calculation for full adder circuit

    Category: Custom IC Design

    By KISHORE085

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    •

    updated over 11 years ago by KISHORE085

    7 replies • 18519 views
  • Discussion

    Virtuoso Editor Tools Menu

    Category: Custom IC Design

    By Octavian

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    •

    updated over 11 years ago by Octavian

    2 replies • 13649 views
  • Discussion

    Parametric analysis - voltage error in the netlist

    Category: Custom IC Design

    By Seokhyun Jeong

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    •

    updated over 11 years ago by Seokhyun Jeong

    2 replies • 924 views
  • Discussion

    RMS jitter from eye diagram

    Category: Custom IC Design

    By 34892

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    •

    updated over 11 years ago by FormerMember

    8 replies • 22611 views
  • Discussion

    Exporting Monte Carlo Simulation

    Category: Custom IC Design

    By parsley

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    •

    updated over 11 years ago by Andrew Beckett

    8 replies • 19696 views
  • Discussion

    Abstract Generator : ERROR (ABS-263): The routing direction for layer M1 is specified but no pitch value is present in the technology file

    Category: Custom IC Design

    By samung

    $usertype

    •

    updated over 11 years ago by samung

    3 replies • 15087 views
  • Discussion

    Abstract Generator : ERROR (ABS-216) [SOLVED], ERROR (ABS-218) [SOLVED], ERROR (ABS-263)

    Category: Custom IC Design

    By samung

    $usertype

    •

    updated over 11 years ago by samung

    6 replies • 17306 views
  • Discussion

    Netlist error when using Global Sources in hierarchy editor

    Category: Custom IC Design

    By EricHsu

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    •

    updated over 11 years ago by Andrew Beckett

    3 replies • 14990 views
  • Discussion

    debug current flows

    Category: Custom IC Design

    By keiichim

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    •

    updated over 11 years ago by PaulCollins

    3 replies • 13613 views
  • Discussion

    Reading signals directly from transient analysis using "psf" command with data in SST2 format

    Category: Custom IC Design

    By vivkr

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    •

    updated over 11 years ago by Andrew Beckett

    9 replies • 7007 views
  • Discussion

    Convergence error in Transient analysis

    Category: Custom IC Design

    By SAMEERGARG

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    •

    updated over 11 years ago by SAMEERGARG

    12 replies • 58047 views
  • Discussion

    Nestlisting failed with ADE XL

    Category: Custom IC Design

    By zczc99

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    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 15762 views
  • Discussion

    I have a design consisting of 32 bit input pin sitimulis problem

    Category: Custom IC Design

    By ahmed osama

    $usertype

    •

    updated over 11 years ago by Andrew Beckett

    10 replies • 17263 views
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