Custom IC Design

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Monte Carlo mismatch on certain instance hierarchy level with Verilog-A model

Category: Custom IC Design

By nthoangga

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updated over 9 years ago by Andrew Beckett

1 replies • 13873 views
Discussion

Cell is not taking variable parameters

Category: Custom IC Design

By RFStuff

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updated over 9 years ago by RFStuff

2 replies • 13789 views
Discussion

Poly to poly capacitor in 0.18 process ?

Category: Custom IC Design

By inessadm

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updated over 9 years ago by Andrew Beckett

1 replies • 13661 views
Discussion

results browser in cadence visualization waveform tool

Category: Custom IC Design

By huadel

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updated over 9 years ago by Andrew Beckett

2 replies • 16082 views
Discussion

Error about extract CDF Parameters of CMOS into Layout

Category: Custom IC Design

By NGO TAN BINH

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updated over 9 years ago by Andrew Beckett

1 replies • 13276 views
Discussion

Switching technology for spectre netlist (Finfet to planar CMOS)

Category: Custom IC Design

By Antouan

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updated over 9 years ago by Andrew Beckett

1 replies • 13414 views
Discussion

Liberate driver waveform

Category: Custom IC Design

By kasula5

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updated over 9 years ago by Andrew Beckett

1 replies • 13317 views
Discussion

ADE_XL active database for multiple sessions

Category: Custom IC Design

By jasongong

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updated over 9 years ago by Andrew Beckett

3 replies • 13594 views
Discussion

Cadence spectre save options are confusing

Category: Custom IC Design

By jasongong

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updated over 9 years ago by Andrew Beckett

3 replies • 22745 views
Discussion

on subharmonic injection VCO phase noise analysis setup

Category: Custom IC Design

By Ruixin

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updated over 9 years ago by Andrew Beckett

1 replies • 13828 views
Discussion

Generate flattened Spectre netlist

Category: Custom IC Design

By ACLI

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updated over 9 years ago by Andrew Beckett

1 replies • 15815 views
Discussion

Virtuoso: Symbol with adjustable ports count

Category: Custom IC Design

By Runner

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updated over 9 years ago by Runner

2 replies • 13756 views
Discussion

LEF file generation problem

Category: Custom IC Design

By Identical

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updated over 9 years ago by Andrew Beckett

1 replies • 13653 views
Discussion

Porting layouts containing Fluid Guard Rings from IC 6.1.5 to IC 6.1.6

Category: Custom IC Design

By Simon C

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updated over 9 years ago by Andrew Beckett

1 replies • 13299 views
Discussion

No Layout Exists for Resistor Cadence Virtuoso

Category: Custom IC Design

By sirtaza

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updated over 9 years ago by Andrew Beckett

3 replies • 18875 views

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