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Custom IC Design

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  • Discussion

    VCAR V11.2.41.500.6.68 hanging-up on command "route 10"

    Category: Custom IC Design

    By lawlag02 lawlag02

    •

    updated over 13 years ago by Quek

    3 replies • 946 views
  • Discussion

    Assura Rules file debuging

    Category: Custom IC Design

    By jmoore jmoore

    •

    updated over 13 years ago by genieQ

    3 replies • 14428 views
  • Discussion

    IC package choice

    Category: Custom IC Design

    By pyohayo pyohayo

    •

    updated over 13 years ago by pyohayo

    11 replies • 16628 views
  • Discussion

    Wrong AC simulation results with MMSIM10 (IC6.14)

    Category: Custom IC Design

    By Kabal Kabal

    •

    updated over 13 years ago by Quek

    1 replies • 12853 views
  • Discussion

    verilog auto-checker search paths

    Category: Custom IC Design

    By markbeck markbeck

    •

    updated over 13 years ago by chrger

    3 replies • 14507 views
  • Discussion

    Is there a way to make Cadence point to the error?

    Category: Custom IC Design

    By tony4tony tony4tony

    •

    updated over 13 years ago by linbo

    7 replies • 17934 views
  • Discussion

    MC string read out

    Category: Custom IC Design

    By Josef Josef

    •

    started over 13 years ago

    0 replies • 12672 views
  • Discussion

    The way to build my own capacitors/resistors

    Category: Custom IC Design

    By DWalter DWalter

    •

    started over 13 years ago

    0 replies • 778 views
  • Discussion

    set design variables in ADE XL

    Category: Custom IC Design

    By nzborsti nzborsti

    •

    updated over 13 years ago by nzborsti

    2 replies • 16019 views
  • Discussion

    TAP cell in 28nm Kit

    Category: Custom IC Design

    By cupidsd cupidsd

    •

    updated over 13 years ago by Quek

    3 replies • 15067 views
  • Discussion

    ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga'

    Category: Custom IC Design

    By Usman001 Usman001

    •

    updated over 13 years ago by Usman001

    2 replies • 8635 views
  • Discussion

    DIVA LVS Error

    Category: Custom IC Design

    By saullacour saullacour

    •

    updated over 13 years ago by Quek

    1 replies • 13547 views
  • Discussion

    [Assura QRC] In what conditions can inductance be extracted?

    Category: Custom IC Design

    By bjbit bjbit

    •

    updated over 13 years ago by Quek

    7 replies • 16060 views
  • Discussion

    Variable priority

    Category: Custom IC Design

    By mailavj mailavj

    •

    started over 13 years ago

    0 replies • 12547 views
  • Discussion

    How to plot gain of OTA in CADENCE spectre

    Category: Custom IC Design

    By ralakhani ralakhani

    •

    started over 13 years ago

    0 replies • 13674 views
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