Custom IC Design

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Discussion

Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett

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started over 14 years ago

0 replies • 29456 views
Discussion

wait a long time to have results updated

Category: Custom IC Design

By sjwprcssw

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started 2 hours ago

0 replies • 21 views
Discussion

Fundamental question on edge phase noise from sampled PNOISE

Category: Custom IC Design

By Yuto Lau

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updated 5 hours ago by Frank Wiedmann

1 replies • 104 views
Discussion

SOA analysis in cadence virtuoso

Category: Custom IC Design

By TUKA

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started 23 hours ago

0 replies • 47 views
Discussion

Strategy for Accelerating Full-Chip AMS Simulation with Multi-Rate Clocks (1kHz / 100MHz)

Category: Custom IC Design

By HY202510149941

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updated 1 day ago by Alonso Schmidt

1 replies • 152 views
Discussion

Buses in spectreText when creating symbol

Category: Custom IC Design

By MC20250412421

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updated 1 day ago by MC20250412421

2 replies • 189 views
Discussion

Replace symbol pin names without changing the pin placement and symbol boundary

Category: Custom IC Design

By SimhanAnalog

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updated 5 days ago by Andrew Beckett

2 replies • 340 views
Discussion

Does Cadence provide a standard Python API for tool automation?

Category: Custom IC Design

By WM20250906725

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updated 5 days ago by Andrew Beckett

5 replies • 1999 views
Discussion

Issue with Skywater 130 Monte Carlo Mismatch Analysis

Category: Custom IC Design

By VLSI lab IITB

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updated 6 days ago by VLSI lab IITB

2 replies • 306 views
Discussion

Issue with the ADE Explorer/Assembler simulator

Category: Custom IC Design

By GL202502244954

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started 6 days ago

0 replies • 110 views
Discussion

Date/time (or $system) in verilogA

Category: Custom IC Design

By leok

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updated 8 days ago by leok

2 replies • 133 views
Discussion

quantus parasitic extraction vs. SKY130 PDK

Category: Custom IC Design

By GS202507021424

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updated 10 days ago by Andrew Beckett

2 replies • 1104 views
Discussion

Quantus Error – Sky130 qrcTechFile not recognized as valid technology file

Category: Custom IC Design

By RK202509013321

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updated 10 days ago by Andrew Beckett

1 replies • 288 views
Discussion

Stop Condition of Liberate trio in characterizing a DFF

Category: Custom IC Design

By TN202507027633

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updated 12 days ago by Guangjun Cao

1 replies • 196 views
Discussion

Noise Results from Transient Noise Simulation and Noise Simulation

Category: Custom IC Design

By Kenny Lu

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updated 13 days ago by Kenny Lu

6 replies • 739 views

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