Custom IC Design

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Symbolic (Analytical) Transfer function from Cadence (XF/PZ) for Simulink modeling

Category: Custom IC Design

By willTspriggs

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updated over 5 years ago by willTspriggs

4 replies • 5980 views
Discussion

VCCAP Usage and Documentation

Category: Custom IC Design

By EEE student

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updated over 5 years ago by EEE student

18 replies • 25939 views
Discussion

Make layout more visible in layout L

Category: Custom IC Design

By BaaB

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updated over 5 years ago by Andrew Beckett

1 replies • 12261 views
Discussion

Can we use $table_model() in verilogAMS

Category: Custom IC Design

By RFStuff

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updated over 5 years ago by Andrew Beckett

3 replies • 13721 views
Discussion

Verilog-A switch model with thermal noise modeling

Category: Custom IC Design

By CatLover

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started over 5 years ago

0 replies • 14528 views
Discussion

Virtuoso 18.1

Category: Custom IC Design

By mooks

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updated over 5 years ago by Andrew Beckett

1 replies • 12662 views
Discussion

How to delete multiple cells in LibManager

Category: Custom IC Design

By HoWei

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updated over 5 years ago by HoWei

2 replies • 15579 views
Discussion

Converting Schematic Testbench Setup into Command Line Spice File(s)?

Category: Custom IC Design

By life

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updated over 5 years ago by Andrew Beckett

1 replies • 1906 views
Discussion

Importing corner setup from CSV with double quotes

Category: Custom IC Design

By Mike Bichan

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updated over 5 years ago by Mike Bichan

4 replies • 13729 views
Discussion

Error in running AMS simulation

Category: Custom IC Design

By rezarmzn

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updated over 5 years ago by rezarmzn

2 replies • 19456 views
Discussion

Howto generate a ibis model from schematic/extracted design

Category: Custom IC Design

By HoWei

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updated over 5 years ago by drdanmc

6 replies • 6725 views
Discussion

Schematic Toolbars

Category: Custom IC Design

By switchy

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updated over 5 years ago by Andrew Beckett

1 replies • 12604 views
Discussion

Liberate System error - could not execute command

Category: Custom IC Design

By Grant Brown

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updated over 5 years ago by bbhav

4 replies • 4973 views
Discussion

Unknown variable appear in ADE window when I run the simulation

Category: Custom IC Design

By Mostafa A

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updated over 5 years ago by Mostafa A

6 replies • 16004 views
Discussion

Importing a VHDL file into Virtuoso for mixed signal sim

Category: Custom IC Design

By FernandoLeite

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updated over 5 years ago by HoWei

6 replies • 21140 views

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