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Custom IC Design

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  • Discussion

    How to get smooth and accurate output waveform without increasing simulation time

    Category: Custom IC Design

    By RFStuff

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    updated over 6 years ago by RFStuff

    9 replies • 20570 views
  • Discussion

    making ruler visible from higher hierarchy

    Category: Custom IC Design

    By FormerMember

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    updated over 6 years ago by FormerMember

    2 replies • 8065 views
  • Discussion

    ViVA ICADV18.1: Hide and unhide subwindows

    Category: Custom IC Design

    By hchan

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    updated over 6 years ago by Andrew Beckett

    1 replies • 13703 views
  • Discussion

    ADE Assembler - Changing the Maximum Jobs while a Run is In Progress

    Category: Custom IC Design

    By Tjaart

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    updated over 6 years ago by Andrew Beckett

    3 replies • 2129 views
  • Discussion

    How to sweep multiple params and save the specific param selected from the circuit?

    Category: Custom IC Design

    By diffsland

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    updated over 6 years ago by FormerMember

    3 replies • 15804 views
  • Discussion

    Launching ADE L failed

    Category: Custom IC Design

    By Chofield

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    updated over 6 years ago by Andrew Beckett

    3 replies • 17325 views
  • Discussion

    How to save subckt parameters in Spectre

    Category: Custom IC Design

    By Dessai

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    updated over 6 years ago by Dessai

    2 replies • 15186 views
  • Discussion

    How to create an output expression for given expression using aged and fresh results

    Category: Custom IC Design

    By noramirkh

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    updated over 6 years ago by noramirkh

    4 replies • 15610 views
  • Discussion

    Hierarchical member access in VerilogA

    Category: Custom IC Design

    By DimitarT

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    updated over 6 years ago by Andrew Beckett

    6 replies • 17467 views
  • Discussion

    Accessing power dissipation in a Verilog module

    Category: Custom IC Design

    By vksinghal

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    updated over 6 years ago by Andrew Beckett

    1 replies • 13912 views
  • Discussion

    Missing point in AMS simulation plot when the value of the consecutive points are same

    Category: Custom IC Design

    By RFStuff

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    updated over 6 years ago by Andrew Beckett

    1 replies • 13939 views
  • Discussion

    Return a string from user-defined function in VerilogA

    Category: Custom IC Design

    By DimitarT

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    updated over 6 years ago by Andrew Beckett

    1 replies • 16534 views
  • Discussion

    Monte Carlo Ocean XL: Interrupting simulations in a script

    Category: Custom IC Design

    By Martyniuk

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    updated over 6 years ago by Andrew Beckett

    1 replies • 14074 views
  • Discussion

    technology file manager

    Category: Custom IC Design

    By skillEater

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    updated over 6 years ago by Andrew Beckett

    3 replies • 15795 views
  • Discussion

    Parameters of a FINFET

    Category: Custom IC Design

    By ElectronLearn

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    updated over 6 years ago by Andrew Beckett

    3 replies • 17947 views
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