Custom IC Design

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Discussion

Liberate AMS: Observation window for async OTP memory

Category: Custom IC Design

By stagro
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updated over 4 years ago by Andrew Beckett

1 replies • 9712 views
Discussion

Cadence schematic showing up all as yellow

Category: Custom IC Design

By Rebekah Zhao
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updated over 4 years ago by Aida

9 replies • 22647 views
Discussion

design/global variable expression

Category: Custom IC Design

By sjwprcker
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updated over 4 years ago by Andrew Beckett

1 replies • 1609 views
Discussion

Weird behavior on "save" statements.

Category: Custom IC Design

By greywanderer
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updated over 4 years ago by greywanderer

6 replies • 2510 views
Discussion

ADE Assembler - calcVal + Monte Carlo + Reusing Trim Codes in new MC for characterization

Category: Custom IC Design

By fyohannes
•
started over 4 years ago

0 replies • 3362 views
Discussion

SPICEIN: How to import mutual inductance K?

Category: Custom IC Design

By acharlet
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updated over 4 years ago by acharlet

7 replies • 15343 views
Discussion

Navigator net highlight/probe and navigator net 'XL status' issue

Category: Custom IC Design

By 94d33m
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started over 4 years ago

0 replies • 1557 views
Discussion

Selecting shapes contained in/inside shape

Category: Custom IC Design

By ajk68
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updated over 4 years ago by ajk68

3 replies • 1847 views
Discussion

Regarding cadence virtuoso installation

Category: Custom IC Design

By Simhadri
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updated over 4 years ago by Andrew Beckett

1 replies • 11397 views
Discussion

[Virtuoso layout XL] How to switch between quick align User Spacing and quick align No Spacing with single keystroke?

Category: Custom IC Design

By 94d33m
•
updated over 4 years ago by Andrew Beckett

3 replies • 16600 views
Discussion

How to run encrypted Pspice model in Cadence?

Category: Custom IC Design

By Firdos
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updated over 4 years ago by Frank Wiedmann

1 replies • 10868 views
Discussion

Relative path for Ocean script in Maestro

Category: Custom IC Design

By FormerMember
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updated over 4 years ago by FormerMember

1 replies • 5148 views
Discussion

skipping digital registers in analog extracted simulations

Category: Custom IC Design

By Mohamayreh
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updated over 4 years ago by FormerMember

1 replies • 9326 views
Discussion

How to keep attached shapes of a multipart path when chopping the multipart path

Category: Custom IC Design

By Strongy2021
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started over 4 years ago

0 replies • 9114 views
Discussion

Simulation of gate leakage current using cadence

Category: Custom IC Design

By Minghao
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updated over 4 years ago by FormerMember

3 replies • 13025 views

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