Custom IC Design

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Discussion

SPICEIN: How to import mutual inductance K?

Category: Custom IC Design

By acharlet
•
updated over 4 years ago by acharlet

7 replies • 15259 views
Discussion

Navigator net highlight/probe and navigator net 'XL status' issue

Category: Custom IC Design

By 94d33m
•
started over 4 years ago

0 replies • 1547 views
Discussion

Selecting shapes contained in/inside shape

Category: Custom IC Design

By ajk68
•
updated over 4 years ago by ajk68

3 replies • 1820 views
Discussion

Regarding cadence virtuoso installation

Category: Custom IC Design

By Simhadri
•
updated over 4 years ago by Andrew Beckett

1 replies • 11349 views
Discussion

[Virtuoso layout XL] How to switch between quick align User Spacing and quick align No Spacing with single keystroke?

Category: Custom IC Design

By 94d33m
•
updated over 4 years ago by Andrew Beckett

3 replies • 16508 views
Discussion

How to run encrypted Pspice model in Cadence?

Category: Custom IC Design

By Firdos
•
updated over 4 years ago by Frank Wiedmann

1 replies • 10819 views
Discussion

Relative path for Ocean script in Maestro

Category: Custom IC Design

By FormerMember
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updated over 4 years ago by FormerMember

1 replies • 5136 views
Discussion

skipping digital registers in analog extracted simulations

Category: Custom IC Design

By Mohamayreh
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updated over 4 years ago by FormerMember

1 replies • 9284 views
Discussion

How to keep attached shapes of a multipart path when chopping the multipart path

Category: Custom IC Design

By Strongy2021
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started over 4 years ago

0 replies • 9074 views
Discussion

Simulation of gate leakage current using cadence

Category: Custom IC Design

By Minghao
•
updated over 4 years ago by FormerMember

3 replies • 12952 views
Discussion

Frequency Measurement when clock is constant (veriloga)

Category: Custom IC Design

By ElZorro
•
started over 4 years ago

0 replies • 10313 views
Discussion

Double sided spectrum in PSS simulation

Category: Custom IC Design

By Alok110
•
updated over 4 years ago by Alok110

3 replies • 10693 views
Discussion

How to snap different layers to the edges of other layers? (Virtuoso Layout XL)

Category: Custom IC Design

By 94d33m
•
started over 4 years ago

0 replies • 10786 views
Discussion

Generating Layout - pcellEvalFailed

Category: Custom IC Design

By nokta
•
updated over 4 years ago by Andrew Beckett

6 replies • 4530 views
Discussion

EMIR simulation fails with EMIR-1099 code

Category: Custom IC Design

By ZMOS
•
started over 4 years ago

0 replies • 9839 views

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