Custom IC Design

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Discussion

systemVerilog equivalent of ahdlLib?

Category: Custom IC Design

By aicdesigner
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updated over 4 years ago by aicdesigner

2 replies • 10515 views
Discussion

How to measure input capacitance?

Category: Custom IC Design

By Holz
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updated over 4 years ago by FormerMember

3 replies • 16132 views
Discussion

PSS and TRAN jitter results not matching for very simplistic testcase

Category: Custom IC Design

By HoWei
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updated over 4 years ago by Frank Wiedmann

19 replies • 17161 views
Discussion

TIMEOUT feature

Category: Custom IC Design

By naga369
•
started over 4 years ago

0 replies • 9795 views
Discussion

PLL + PSS + PNOISE convergence

Category: Custom IC Design

By HoWei
•
updated over 4 years ago by FormerMember

17 replies • 24702 views
Discussion

How to treat parasitic device as open for LVS

Category: Custom IC Design

By brianbranch
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updated over 4 years ago by Andrew Beckett

1 replies • 10548 views
Discussion

WARNING (OCN-6038) Results dc are not available loading OCEAN script

Category: Custom IC Design

By Victor Camacho
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updated over 4 years ago by Andrew Beckett

3 replies • 11676 views
Discussion

Report CPU time directly in ADE Assembler

Category: Custom IC Design

By jehh
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updated over 4 years ago by Frank Wiedmann

3 replies • 9907 views
Discussion

Plotting phase spectrum

Category: Custom IC Design

By sidt
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updated over 4 years ago by sidt

2 replies • 13798 views
Discussion

Post Layout simulation accuracy

Category: Custom IC Design

By Fatima65
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updated over 4 years ago by Frank Wiedmann

7 replies • 13509 views
Discussion

Virtuoso Cadence crashes when opening layout viewer

Category: Custom IC Design

By Eric2020
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updated over 4 years ago by Andrew Beckett

1 replies • 10527 views
Discussion

How can I enlarge the result window in the horizontal axis direction?

Category: Custom IC Design

By yysunj
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updated over 4 years ago by Andrew Beckett

1 replies • 10042 views
Discussion

Abstract Generator : ERROR (ABS-20024)

Category: Custom IC Design

By Chan ho
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updated over 4 years ago by Andrew Beckett

1 replies • 10006 views
Discussion

How can I save the converged values at the nodes after the last iteration of the time step in verilog-A?

Category: Custom IC Design

By rhanna
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updated over 4 years ago by rhanna

6 replies • 11243 views
Discussion

Time domain simulation of switched capacitor circuits

Category: Custom IC Design

By Svilen64
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updated over 4 years ago by Andrew Beckett

1 replies • 10271 views

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