Custom IC Design

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Discussion

ocean run() recreates netlist

Category: Custom IC Design

By kkdesbois

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updated over 2 years ago by kkdesbois

2 replies • 5364 views
Discussion

deepprobe to access systemVerilog variables

Category: Custom IC Design

By ElZorro

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started over 2 years ago

0 replies • 5314 views
Discussion

Load pull contour plot error

Category: Custom IC Design

By Martinsh

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started over 2 years ago

0 replies • 5102 views
Discussion

Increasing the max jobs using ocean script.

Category: Custom IC Design

By Sathvik Bhargav

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updated over 2 years ago by Andrew Beckett

1 replies • 5383 views
Discussion

Can university users use https://support.cadence.com website?

Category: Custom IC Design

By wangyunxin

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updated over 2 years ago by Andrew Beckett

1 replies • 1045 views
Discussion

Equation based Sparameters

Category: Custom IC Design

By ChrisTower

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started over 2 years ago

0 replies • 4816 views
Discussion

Using extracted view with iterated instance

Category: Custom IC Design

By Mathieu Chene

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updated over 2 years ago by Mathieu Chene

2 replies • 5849 views
Discussion

Creating vector variable in ADE XL to configure Verilog-A module

Category: Custom IC Design

By RaffaeleUdS

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updated over 2 years ago by Andrew Beckett

1 replies • 5593 views
Discussion

Any way to set a default value for the design variables in ADE explorer

Category: Custom IC Design

By jason1127

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updated over 2 years ago by Andrew Beckett

1 replies • 5518 views
Discussion

Previously closed windows minimize upon reopening in IC23.10

Category: Custom IC Design

By LMendolia

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updated over 2 years ago by Andrew Beckett

1 replies • 5616 views
Discussion

How to repair miscalculated bBox of an object that I cannot spot on the layout?

Category: Custom IC Design

By MichalWolodzko

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updated over 2 years ago by MichalWolodzko

2 replies • 5664 views
Discussion

Simulation temerature dependent on DC power

Category: Custom IC Design

By Martinsh

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updated over 2 years ago by ShawnLogan

7 replies • 6750 views
Discussion

Cadence Layout DRC Pins Error

Category: Custom IC Design

By Sarah1898

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updated over 2 years ago by ShawnLogan

4 replies • 8330 views
Discussion

Align hierarchic pins in layout with SKILL script.

Category: Custom IC Design

By MichalWolodzko

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started over 2 years ago

0 replies • 5114 views
Discussion

scaling and DBU/UU - XStream vs XOasis

Category: Custom IC Design

By vshih

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updated over 2 years ago by Andrew Beckett

1 replies • 1598 views

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