Custom IC Design

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Discussion

Layout Dummy filling using Assura in Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

4 replies • 11366 views
Discussion

Parameter 'ad' not found in transistor models

Category: Custom IC Design

By Vikram17

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started over 3 years ago

0 replies • 488 views
Discussion

The cell is getting skipped during cell characterization

Category: Custom IC Design

By Vikram17

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started over 3 years ago

0 replies • 8461 views
Discussion

What the license is required in spectre simulation?

Category: Custom IC Design

By ichiro

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updated over 3 years ago by ichiro

2 replies • 11746 views
Discussion

Gravity snapping through hierarchy

Category: Custom IC Design

By anomolousDoug

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updated over 3 years ago by Andrew Beckett

1 replies • 8812 views
Discussion

Output expressions from Data Browser VIVA vs. Calculator

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 8865 views
Discussion

Using the same output expressions for post-layout simulation

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

3 replies • 9172 views
Discussion

extracting simulation temperature

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Svilen64

2 replies • 10281 views
Discussion

Describe the peak current method [Verilog-A]

Category: Custom IC Design

By YYLee

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updated over 3 years ago by FormerMember

2 replies • 8916 views
Discussion

How to set appropriate transient simulation step size?

Category: Custom IC Design

By Clara Dong

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updated over 3 years ago by Andrew Beckett

1 replies • 14292 views
Discussion

What is the correct way to make a cellview from DSPF file?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

2 replies • 10236 views
Discussion

Verilog-A control of temperature for single instances?

Category: Custom IC Design

By PistakioKernel

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updated over 3 years ago by PistakioKernel

2 replies • 9415 views
Discussion

Spectre failed to complete the simulation with Error ID=5011

Category: Custom IC Design

By shbmsra12

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updated over 3 years ago by FormerMember

7 replies • 6253 views
Discussion

Custom vs PNR layout

Category: Custom IC Design

By StephanieIFX

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updated over 3 years ago by Andrew Beckett

1 replies • 8847 views
Discussion

SystemVerilog Outputs Incorrect Real Datatype Number Precision

Category: Custom IC Design

By Nader Fathy

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updated over 3 years ago by Andrew Beckett

2 replies • 10410 views

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