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Custom IC Design

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  • Discussion

    trapezoidal ringing with spectreX

    Category: Custom IC Design

    By sjwprcker

    •

    updated over 3 years ago by sjwprcker

    6 replies • 19277 views
  • Discussion

    Cadence Vrituoso

    Category: Custom IC Design

    By younghyun

    •

    updated over 3 years ago by pengchaoqun

    6 replies • 13281 views
  • Discussion

    Dc operating point info with spectre -X LX

    Category: Custom IC Design

    By sv srini

    •

    started over 3 years ago

    0 replies • 2075 views
  • Discussion

    how to include the verilogA content in the netlist

    Category: Custom IC Design

    By sjwprcker

    •

    updated over 3 years ago by sjwprcker

    7 replies • 15139 views
  • Discussion

    Voltage jump in transient noise simulation when reading data from file

    Category: Custom IC Design

    By thegon

    •

    updated over 3 years ago by FormerMember

    3 replies • 12066 views
  • Discussion

    Virtuoso Constraints SKILL code: correct my cstFindFirstConstraint syntax

    Category: Custom IC Design

    By dfink

    •

    updated over 3 years ago by dfink

    3 replies • 10458 views
  • Discussion

    synthesizing Verilog code in Cadence Virtuoso

    Category: Custom IC Design

    By Senan

    •

    updated over 4 years ago by Senan

    2 replies • 12533 views
  • Discussion

    Cellview generation from VHDL code in cadence 618

    Category: Custom IC Design

    By rovin

    •

    updated over 4 years ago by rovin

    5 replies • 13083 views
  • Discussion

    .csv output in spectre

    Category: Custom IC Design

    By Yea Chul

    •

    updated over 4 years ago by HTTb

    11 replies • 15604 views
  • Discussion

    Number of Harmonics in PSS analysis to determine the maximum time step

    Category: Custom IC Design

    By RFGeek

    •

    updated over 4 years ago by FormerMember

    2 replies • 12272 views
  • Discussion

    maestro spectre parallel jobs reduce as total jobs neared

    Category: Custom IC Design

    By Pirate King

    •

    started over 4 years ago

    0 replies • 9267 views
  • Discussion

    way to set timer length in verilog-A

    Category: Custom IC Design

    By sjwprcker

    •

    started over 4 years ago

    0 replies • 9726 views
  • Discussion

    difference between "temp" & "tnom"

    Category: Custom IC Design

    By sjwprcker

    •

    updated over 4 years ago by sjwprcker

    2 replies • 4518 views
  • Discussion

    Using 'm' multiplier or vector/array notation for MonteCarlo simulations

    Category: Custom IC Design

    By vpreuss

    •

    updated over 4 years ago by vpreuss

    2 replies • 3157 views
  • Discussion

    how to set the env hed.checks?

    Category: Custom IC Design

    By sjwprcker

    •

    updated over 4 years ago by sjwprcker

    2 replies • 9643 views
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