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Custom IC Design

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  • Discussion

    Model parameters clarity

    Category: Custom IC Design

    By shashwatss

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    updated over 4 years ago by Andrew Beckett

    1 replies • 12350 views
  • Discussion

    How can I solve the "ERROR (VIVA-9000)" ?

    Category: Custom IC Design

    By ichiro

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    updated over 4 years ago by ichiro

    6 replies • 5386 views
  • Discussion

    parasitic extraction on "updated" schematics

    Category: Custom IC Design

    By life

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    •

    updated over 4 years ago by FormerMember

    1 replies • 1256 views
  • Discussion

    Any bindkey to run "netlist -> recreate"?

    Category: Custom IC Design

    By sjwprcker

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    •

    updated over 4 years ago by sjwprcker

    4 replies • 1599 views
  • Discussion

    Suppress: *WARNING* COMBINE attribute library not defined

    Category: Custom IC Design

    By Aldo2

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    updated over 4 years ago by Andrew Beckett

    18 replies • 24202 views
  • Discussion

    ADE Explorer - Spec Pass/Fail

    Category: Custom IC Design

    By life

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    •

    updated over 4 years ago by life

    1 replies • 2403 views
  • Discussion

    Update W/L number in instance property, but resistor "r "value isn't change accordingly

    Category: Custom IC Design

    By ringamp

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    updated over 4 years ago by ringamp

    2 replies • 2346 views
  • Discussion

    Can I use a variable as interpolation point in the value function?

    Category: Custom IC Design

    By maaz2020

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    updated over 4 years ago by maaz2020

    5 replies • 14704 views
  • Discussion

    Verilog-AMS Simulation speed issue while using $table_model for reading from a file.

    Category: Custom IC Design

    By RFStuff

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    updated over 4 years ago by Andrew Beckett

    1 replies • 10957 views
  • Discussion

    How to pass a real array as an input argument to a function in Verilog (in AMS simulation)

    Category: Custom IC Design

    By RFStuff

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    updated over 4 years ago by RFStuff

    2 replies • 12299 views
  • Discussion

    Restrict ICPR SGE Job to only run 1 simulation point (ADE Assembler)

    Category: Custom IC Design

    By jehh

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    updated over 4 years ago by Andrew Beckett

    1 replies • 11999 views
  • Discussion

    How can I fix the error in my simulation?

    Category: Custom IC Design

    By yysunj

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    updated over 4 years ago by Andrew Beckett

    3 replies • 12629 views
  • Discussion

    Using FinFETs in OrCAD Capture

    Category: Custom IC Design

    By Sati

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    updated over 4 years ago by Sati

    2 replies • 11423 views
  • Discussion

    Question on PSS+PNoise simulation for a Track and Hold circuit

    Category: Custom IC Design

    By YutaoLiu

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    updated over 4 years ago by Andrew Beckett

    11 replies • 14655 views
  • Discussion

    Post Layout simulation for multi-finger transistors

    Category: Custom IC Design

    By Senan

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    •

    updated over 4 years ago by FormerMember

    11 replies • 15788 views
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