Custom IC Design

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Discussion

Using DFT to analyze a time-interleaving track and hold circuit

Category: Custom IC Design

By YutaoLiu

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updated over 5 years ago by Andrew Beckett

1 replies • 14054 views
Discussion

How do make the clock 25% duty cycle with jitter capability

Category: Custom IC Design

By cADEUser

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updated over 5 years ago by Andrew Beckett

4 replies • 16904 views
Discussion

How to generate a clock signal with random noise in Cadence Spectre?

Category: Custom IC Design

By BackerShu

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updated over 5 years ago by Andrew Beckett

3 replies • 28872 views
Discussion

Method to scale up or down lots of resistor/capacitor value together

Category: Custom IC Design

By FormerMember

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updated over 5 years ago by henker

1 replies • 2280 views
Discussion

Mixed-signal CDL netlist export

Category: Custom IC Design

By Nicolas Callens

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updated over 5 years ago by Andrew Beckett

1 replies • 15068 views
Discussion

LDO design and simulation

Category: Custom IC Design

By SHATADAL IIITG

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started over 5 years ago

0 replies • 13888 views
Discussion

Smooth dynamic parameter variation in transient sim

Category: Custom IC Design

By Quantum7

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updated over 5 years ago by Andrew Beckett

1 replies • 14962 views
Discussion

Plotting temperature in a transient simulation

Category: Custom IC Design

By Quantum7

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updated over 5 years ago by Quantum7

9 replies • 20461 views
Discussion

Pin placement does not show up

Category: Custom IC Design

By Nicolas Callens

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updated over 5 years ago by Andrew Beckett

1 replies • 13968 views
Discussion

How to fix "*WARNING* file /home/Kaveri/CDS.log Malformed Lock-Stake file.", when running virtuoso?

Category: Custom IC Design

By Marben

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updated over 5 years ago by Marben

2 replies • 9359 views
Discussion

Is CDL netlist *.PININFO pin1:O pin2:I pin3:IO property a syntax requirement?

Category: Custom IC Design

By max123321

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updated over 5 years ago by Andrew Beckett

3 replies • 3290 views
Discussion

VerilogA

Category: Custom IC Design

By Suhas7

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updated over 5 years ago by Andrew Beckett

1 replies • 13828 views
Discussion

spiceText view with AMS OSS netlister

Category: Custom IC Design

By RobinC

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updated over 5 years ago by Andrew Beckett

3 replies • 14764 views
Discussion

Input Capacitance Measurements of Digital Cells in Cadence Liberate

Category: Custom IC Design

By anurans

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updated over 5 years ago by anurans

8 replies • 17266 views
Discussion

Negative Power Numbers During the Synthesis Over a Custom Cell Library (Liberate)

Category: Custom IC Design

By anurans

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updated over 5 years ago by Guangjun Cao

2 replies • 15714 views

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