Custom IC Design

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ade-xl with two schematics/simulations (same nets names), how to know which schematic the VT("X") refer to

Category: Custom IC Design

By monglebest

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updated over 7 years ago by Andrew Beckett

3 replies • 1825 views
Discussion

Noise simulation wrong

Category: Custom IC Design

By LukiLeu

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updated over 7 years ago by Andrew Beckett

5 replies • 14723 views
Discussion

spectre simulator options in spice language

Category: Custom IC Design

By John Barth

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updated over 7 years ago by John Barth

2 replies • 17461 views
Discussion

Check Mosfet operation region with Checks/Asserts

Category: Custom IC Design

By LukiLeu

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updated over 7 years ago by Andrew Beckett

9 replies • 5479 views
Discussion

aligning eye diagrams across corners

Category: Custom IC Design

By KurtKimber1

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updated over 7 years ago by KurtKimber1

4 replies • 14544 views
Discussion

Sorting ADE-Xl Results tab rows across >1 columns

Category: Custom IC Design

By fortune100worse

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updated over 7 years ago by fortune100worse

2 replies • 2409 views
Discussion

any specific env var to control "Only check views with explicit pin order" in VSE Cross-View Checker?

Category: Custom IC Design

By zssfred

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updated over 7 years ago by zssfred

2 replies • 1264 views
Discussion

Voltus-FI: How to automate the creation of selfheating-aware EM/IR text reports after every run

Category: Custom IC Design

By hchan

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updated over 7 years ago by Saloni Chhabra

29 replies • 16497 views
Discussion

error of failed request

Category: Custom IC Design

By jmcal

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updated over 7 years ago by Marc Heise

8 replies • 16159 views
Discussion

Inherited Connections - connecting to nets

Category: Custom IC Design

By kash022

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updated over 7 years ago by Marc Heise

1 replies • 7459 views
Discussion

undefined function uiLoadTrigger in si.log

Category: Custom IC Design

By zssfred

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updated over 7 years ago by zssfred

19 replies • 21028 views
Discussion

[Maestro] Expression to check whether an asset has been violated in a simulation

Category: Custom IC Design

By PatrikOsgnach

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updated over 7 years ago by PatrikOsgnach

7 replies • 19876 views
Discussion

how to have CLASS BUMP statement under the PORT statement in LEF ?

Category: Custom IC Design

By RoseRivera

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started over 7 years ago

0 replies • 1459 views
Discussion

Generate LEF file through Script

Category: Custom IC Design

By Ishant Anand

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updated over 7 years ago by Andrew Beckett

3 replies • 16499 views
Discussion

VerilogA code error:signal exceeds blowup limit

Category: Custom IC Design

By Sandeep4386

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updated over 7 years ago by Sandeep4386

6 replies • 9790 views

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