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Custom IC Design

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  • Discussion

    I am not able to select the layer while drawing a wire or a bus in Layout.

    Category: Custom IC Design

    By skillEater

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    updated 29 days ago by RobMan

    1 replies • 1024 views
  • Discussion

    How to mute WARNING This OS does not appear to be a Cadence supported Linux configuration

    Category: Custom IC Design

    By ebecheto

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    updated 1 month ago by Andrew Beckett

    1 replies • 952 views
  • Discussion

    Modgen: How to add dummy FETs sharing diffusion without issues of marker layers?

    Category: Custom IC Design

    By sceekr

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    started 1 month ago

    0 replies • 1161 views
  • Discussion

    gsclib090 (gpdk090 standard cell library) download?

    Category: Custom IC Design

    By GS202507021424

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    •

    updated 1 month ago by RobMan

    1 replies • 1471 views
  • Discussion

    Problem with ADE Explorer and spectre_encrypt (IC 21.1 ISR22)

    Category: Custom IC Design

    By GL202502244954

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    •

    started 1 month ago

    0 replies • 1187 views
  • Discussion

    Using VCSV File in Spectre Simulation

    Category: Custom IC Design

    By aalbason

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    •

    updated 1 month ago by aalbason

    2 replies • 1909 views
  • Discussion

    Quantus PVS Parasitic Extraction ERROR (LBRCXM-992)

    Category: Custom IC Design

    By RV202509139743

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    •

    started 1 month ago

    0 replies • 955 views
  • Discussion

    Maestro ERROR for bus ">" when plot signals

    Category: Custom IC Design

    By LH202509171654

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    •

    started 1 month ago

    0 replies • 582 views
  • Discussion

    Effect of Large Voltage (1 MV) on Accuracy When Using relref=sigglobal in Spectre APS/X

    Category: Custom IC Design

    By ycyang

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    •

    started 1 month ago

    0 replies • 786 views
  • Discussion

    Missing instance on LVS (IOs)

    Category: Custom IC Design

    By RV202509139743

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    •

    started 1 month ago

    0 replies • 993 views
  • Discussion

    Unmatched schematic pin label

    Category: Custom IC Design

    By RV202509139743

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    •

    updated 1 month ago by RobMan

    1 replies • 1409 views
  • Discussion

    schViewToView symbol creation from systemverilog not working

    Category: Custom IC Design

    By SimhanAnalog

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    •

    updated 1 month ago by rajeshcad

    9 replies • 3097 views
  • Discussion

    .proc file for TSMC65 for the EMX simulator

    Category: Custom IC Design

    By GL202502244954

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    •

    updated 1 month ago by GL202502244954

    4 replies • 2168 views
  • Discussion

    new DRC rule(s) added to new(er) gpdk045 versions?

    Category: Custom IC Design

    By GS202507021424

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    •

    updated 1 month ago by Andrew Beckett

    1 replies • 971 views
  • Discussion

    Does Cadence provide a standard Python API for tool automation?

    Category: Custom IC Design

    By WM20250906725

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    •

    updated 1 month ago by Andrew Beckett

    3 replies • 1788 views
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