Custom IC Design

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Discussion

Use of DC operating point parameters in calculations and plots

Category: Custom IC Design

By archive

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updated over 8 years ago by Andrew Beckett

13 replies • 25579 views
Discussion

QPSK modulated signal

Category: Custom IC Design

By EngrZM

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updated over 8 years ago by EngrZM

2 replies • 14337 views
Discussion

Is there any way to use assura compatible file (*.drc , *.lvs ) file in PVS plugin (*.pvl)

Category: Custom IC Design

By Anklon

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updated over 8 years ago by Andrew Beckett

1 replies • 14120 views
Discussion

ADE L error

Category: Custom IC Design

By Anklon

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updated over 8 years ago by Andrew Beckett

1 replies • 16137 views
Discussion

Environment variable to prevent "stream in translation complete" pop up dialogue after streamout and streamin

Category: Custom IC Design

By blankman

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updated over 8 years ago by blankman

2 replies • 1150 views
Discussion

How to plot transistor's parameters evolution over time with transient simulation

Category: Custom IC Design

By Edouard R

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updated over 8 years ago by Edouard R

3 replies • 5364 views
Discussion

PEX Compilation Error

Category: Custom IC Design

By mehdina94rm

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updated over 8 years ago by marten

2 replies • 15623 views
Discussion

How to fix warning from Spectre about a missing bulk-source and bulk-drain diode?

Category: Custom IC Design

By Bean Nakamura

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updated over 8 years ago by taraRF

3 replies • 15599 views
Discussion

installation issue in Installscape through DVD

Category: Custom IC Design

By conrel

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updated over 8 years ago by Andrew Beckett

1 replies • 13934 views
Discussion

" *Error* asiGetDesignLibName: no applicable method for the class - list" during parametric simulation in ADE

Category: Custom IC Design

By yayla

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updated over 8 years ago by Andrew Beckett

6 replies • 5558 views
Discussion

Convergence difficulties in Verilog A while using equivalent differential equation instead of laplace_nd function

Category: Custom IC Design

By Quilon

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updated over 8 years ago by Andrew Beckett

3 replies • 15518 views
Discussion

Virtuoso Layout XL/GXL -- rasterizing an anyAngle polygon onto a grid

Category: Custom IC Design

By jack.holloway

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updated over 8 years ago by MarkRuiter

2 replies • 2994 views
Discussion

CDS_thru, LVS, new layer

Category: Custom IC Design

By samer1

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updated over 8 years ago by samer1

3 replies • 14936 views
Discussion

varying inline subckt parameter with altergroup in Spectre

Category: Custom IC Design

By sunilm123

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updated over 8 years ago by Andrew Beckett

1 replies • 15040 views
Discussion

$system() command in Verilog-A

Category: Custom IC Design

By farhan89

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updated over 8 years ago by Andrew Beckett

1 replies • 14319 views

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Custom IC Design

Latest Posts

Use of DC operating point parameters in calculations and plots

QPSK modulated signal

Is there any way to use assura compatible file (.drc , .lvs ) file in PVS plugin (*.pvl)

ADE L error

Environment variable to prevent "stream in translation complete" pop up dialogue after streamout and streamin

How to plot transistor's parameters evolution over time with transient simulation

PEX Compilation Error

How to fix warning from Spectre about a missing bulk-source and bulk-drain diode?

installation issue in Installscape through DVD

" Error asiGetDesignLibName: no applicable method for the class - list" during parametric simulation in ADE

Convergence difficulties in Verilog A while using equivalent differential equation instead of laplace_nd function

Virtuoso Layout XL/GXL -- rasterizing an anyAngle polygon onto a grid

CDS_thru, LVS, new layer

varying inline subckt parameter with altergroup in Spectre

$system() command in Verilog-A

Community Guidelines