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Custom IC Design

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  • Discussion

    How to find the mobility of mos in 45nm technology library

    Category: Custom IC Design

    By vinod joshi

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    updated over 9 years ago by Andrew Beckett

    1 replies • 20566 views
  • Discussion

    How to simulate initial condition for post-layout simulation?

    Category: Custom IC Design

    By BaaB

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    updated over 9 years ago by Andrew Beckett

    1 replies • 14303 views
  • Discussion

    Problem in Monte Carlo with XPS MS

    Category: Custom IC Design

    By rsashwinkumar

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    updated over 9 years ago by Andrew Beckett

    1 replies • 14215 views
  • Discussion

    Simulate all possible value of a MOSFET threshold voltage

    Category: Custom IC Design

    By BaaB

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    •

    updated over 9 years ago by BaaB

    4 replies • 14637 views
  • Discussion

    How to parameterize a string parameter in ADE XL?

    Category: Custom IC Design

    By rickyuexu

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    started over 9 years ago

    0 replies • 13527 views
  • Discussion

    Assura QRC Error

    Category: Custom IC Design

    By sdineshkumar

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    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 15949 views
  • Discussion

    select master cell in ADEXL

    Category: Custom IC Design

    By Clidre

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 12954 views
  • Discussion

    Extracting Interconnect Parameters

    Category: Custom IC Design

    By rafaelon

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    •

    updated over 9 years ago by rafaelon

    2 replies • 13330 views
  • Discussion

    Error during the RC extraction using 45 nm technology

    Category: Custom IC Design

    By vinod joshi

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 13269 views
  • Discussion

    lineread command error out when trying to read a verilog generation log file

    Category: Custom IC Design

    By mlea

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    updated over 9 years ago by Andrew Beckett

    1 replies • 13382 views
  • Discussion

    Pass Path and Filename via Variable in ADEXL

    Category: Custom IC Design

    By SebastianS

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    started over 9 years ago

    0 replies • 14680 views
  • Discussion

    "FATAL: Insufficient memory available" spectre issue

    Category: Custom IC Design

    By Dresdener

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    •

    updated over 9 years ago by Dresdener

    2 replies • 6175 views
  • Discussion

    Help with Verilog-A file operation tasks

    Category: Custom IC Design

    By Reks

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 14232 views
  • Discussion

    Sweep vth values

    Category: Custom IC Design

    By syafiq

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    •

    updated over 9 years ago by Andrew Beckett

    4 replies • 13848 views
  • Discussion

    preferred way to sweep temperature in ADEXL

    Category: Custom IC Design

    By danmc91

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 21225 views
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