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Custom IC Design

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  • Discussion

    Verilog IN error

    Category: Custom IC Design

    By magarwal

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 18047 views
  • Discussion

    Post-layout simulation with Parasitic R

    Category: Custom IC Design

    By Monady

    •

    started over 9 years ago

    0 replies • 16300 views
  • Discussion

    LayoutXL stop layers

    Category: Custom IC Design

    By PNadeau

    •

    updated over 9 years ago by PNadeau

    3 replies • 16574 views
  • Discussion

    Calculator -> Using 'value' in equation

    Category: Custom IC Design

    By syafiq

    •

    updated over 9 years ago by syafiq

    6 replies • 20367 views
  • Discussion

    ADEXL Direct Plot error

    Category: Custom IC Design

    By PNadeau

    •

    updated over 9 years ago by PNadeau

    4 replies • 16550 views
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    noise summary parameters and noise simualtions

    Category: Custom IC Design

    By Jeni

    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 18464 views
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    Cadence and Windows

    Category: Custom IC Design

    By manudupouy

    •

    updated over 9 years ago by manudupouy

    2 replies • 20665 views
  • Discussion

    Maximum value of measurements set on Calculator

    Category: Custom IC Design

    By Johanny Saenz

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 23668 views
  • Discussion

    Add pins and pin names quickly to symbol

    Category: Custom IC Design

    By Tobben24

    •

    updated over 9 years ago by SteveRFIC

    4 replies • 23711 views
  • Discussion

    Plotting the DC sweep but clipped

    Category: Custom IC Design

    By Pyroblast

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 15839 views
  • Discussion

    ADEXL - Using initial conditions from a first sim in a second sim

    Category: Custom IC Design

    By cdonovan

    •

    updated over 9 years ago by cdonovan

    4 replies • 4732 views
  • Discussion

    How do I save/sweep dc operating points via Jazz?

    Category: Custom IC Design

    By KH28

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 1538 views
  • Discussion

    How to streamout a gds and will have an output that is flattened

    Category: Custom IC Design

    By jorenrefuerzo

    •

    updated over 9 years ago by Andrew Beckett

    9 replies • 24654 views
  • Discussion

    layout XL - flag drawing touching blockage?

    Category: Custom IC Design

    By yeh1

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 1089 views
  • Discussion

    Using ALTER statement in ADEL/XL

    Category: Custom IC Design

    By AlbertoGS

    •

    updated over 9 years ago by Andrew Beckett

    6 replies • 4653 views
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