Custom IC Design

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Discussion

Gain peaking in TIA

Category: Custom IC Design

By TUKA
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updated over 2 years ago by TUKA

4 replies • 7675 views
Discussion

how to simulate spatial variation to see benefit of common centroid layout

Category: Custom IC Design

By supriyo1985
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updated over 2 years ago by supriyo1985

2 replies • 6139 views
Discussion

way to run dm & cm stb in one simulation

Category: Custom IC Design

By sjwprcker
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started over 2 years ago

0 replies • 762 views
Discussion

dft and psd function in viva

Category: Custom IC Design

By sjwprcker
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updated over 2 years ago by Andrew Beckett

5 replies • 7840 views
Discussion

environment variable to enable LSCS

Category: Custom IC Design

By sjwprcker
•
updated over 2 years ago by sjwprcker

5 replies • 7083 views
Discussion

Dynamic Temperature Simulation

Category: Custom IC Design

By illaoi
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updated over 2 years ago by ShawnLogan

1 replies • 6089 views
Discussion

Waiting for available license for Virtuoso(R) Spectre

Category: Custom IC Design

By yip111
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updated over 2 years ago by ShawnLogan

1 replies • 1361 views
Discussion

sim error when running sp simulation

Category: Custom IC Design

By TommasoF
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updated over 2 years ago by TommasoF

3 replies • 8540 views
Discussion

use $cds_set_temperature in verilogams report “...libvpi.so...” error

Category: Custom IC Design

By Ring Lewis
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started over 2 years ago

0 replies • 5710 views
Discussion

Where is SMG "schematic model generator“ in IC618

Category: Custom IC Design

By SpiceMonkey
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updated over 2 years ago by Andrew Beckett

1 replies • 1039 views
Discussion

B1f and K in sp Analysis

Category: Custom IC Design

By illaoi
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updated over 2 years ago by ShawnLogan

1 replies • 6802 views
Discussion

How to copy designs to different machines?

Category: Custom IC Design

By Doronzzz
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updated over 2 years ago by ShawnLogan

3 replies • 7081 views
Discussion

ADE: Need a trick for plotting result values vs corners

Category: Custom IC Design

By StephanWeber
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updated over 2 years ago by Andrew Beckett

1 replies • 5757 views
Discussion

"Fixed Parameter" option in "Detail - Transpose" Virtuoso results display - unexpected behavior

Category: Custom IC Design

By shlomo34
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updated over 2 years ago by shlomo34

1 replies • 1594 views
Discussion

Limiting the length of a vector in VIVA

Category: Custom IC Design

By CSCNalu
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updated over 2 years ago by Andrew Beckett

1 replies • 5540 views

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