Custom IC Design

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Discussion

Designing a Two stage CMOS OP Amp using Cadence Virtuoso_hspiceD simulator

Category: Custom IC Design

By Indhu Sekar
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updated over 2 years ago by Andrew Beckett

11 replies • 14061 views
Discussion

Spice In with CDL netlist issue

Category: Custom IC Design

By AutoJeff
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started over 2 years ago

0 replies • 7785 views
Discussion

Calculation of noise multiplication factor (γ) for Ring VCO

Category: Custom IC Design

By Upendra Ch
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updated over 2 years ago by Upendra Ch

5 replies • 7958 views
Discussion

Pin Creation Issue in Virtuoso Layout

Category: Custom IC Design

By POCHAMREDDY
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updated over 2 years ago by RobMan

4 replies • 7758 views
Discussion

Download older version QUANTUS211

Category: Custom IC Design

By zhliang
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updated over 2 years ago by mschw

1 replies • 6035 views
Discussion

Making Spiral Inductor Layout for EM simulations:

Category: Custom IC Design

By Upendra Ch
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updated over 2 years ago by Upendra Ch

4 replies • 8029 views
Discussion

EVM Measurement (envlp analysis)

Category: Custom IC Design

By illaoi
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updated over 2 years ago by illaoi

3 replies • 7641 views
Discussion

Verilog-A: is it possible to nest analog events? e.g. timer() inside cross()?

Category: Custom IC Design

By dontpanic
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updated over 2 years ago by Andrew Beckett

1 replies • 9273 views
Discussion

Veriloga model of load behaves differently when standalone or instantiated with other circuit

Category: Custom IC Design

By unSkilled
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updated over 2 years ago by Andrew Beckett

2 replies • 6584 views
Discussion

Virtuoso ADE SKILL Reference ICADVM20.1: calcVal on a transient expression does not work

Category: Custom IC Design

By NewScreenName
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updated over 2 years ago by Andrew Beckett

1 replies • 6549 views
Discussion

About tsmc65 .proc file:

Category: Custom IC Design

By Upendra Ch
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updated over 2 years ago by Andrew Beckett

1 replies • 8189 views
Discussion

VerilogA simulation error

Category: Custom IC Design

By TUKA
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updated over 2 years ago by TUKA

4 replies • 7061 views
Discussion

issue with assembler running corner simulations

Category: Custom IC Design

By greywanderer
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updated over 2 years ago by Andrew Beckett

1 replies • 5852 views
Discussion

How to derive edge phase noise from Output Noise in sampled Pnoise simulation

Category: Custom IC Design

By mxm14
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updated over 2 years ago by Frank Wiedmann

11 replies • 14254 views
Discussion

Catch glitches on DC signal.

Category: Custom IC Design

By IKIF
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updated over 2 years ago by ShawnLogan

3 replies • 6215 views

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