Custom IC Design

Latest Posts

Discussion

how to set the default number of digits in the sim log

Category: Custom IC Design

By sjwprcker
•
updated over 2 years ago by sjwprcker

2 replies • 6722 views
Discussion

will the phase of the pss period affect sampled pnoise result? can I control the pss phase?

Category: Custom IC Design

By Ring Lewis
•
updated over 2 years ago by Ring Lewis

2 replies • 6980 views
Discussion

Running corner PVT sims with scalar output evaluated but waveforms not saved

Category: Custom IC Design

By SunnyBhagia
•
updated over 2 years ago by ShawnLogan

4 replies • 7277 views
Discussion

error in digital verilog code

Category: Custom IC Design

By blossom
•
updated over 2 years ago by Andrew Beckett

2 replies • 8118 views
Discussion

How to replace the device instance numbers

Category: Custom IC Design

By ichiro
•
updated over 2 years ago by Andrew Beckett

3 replies • 7032 views
Discussion

Font Size for Trace Info Overlay in ViVA

Category: Custom IC Design

By jdsherman
•
updated over 2 years ago by Andrew Beckett

2 replies • 6467 views
Discussion

RFpro-cadence interface

Category: Custom IC Design

By SreekanthIISc
•
updated over 2 years ago by engrvip

2 replies • 7592 views
Discussion

QRC error undefined symbol: _ztin12openaccess_418oaconflictobserverins_8oaappdefelj0eee

Category: Custom IC Design

By KhaledHasan
•
updated over 2 years ago by Andrew Beckett

1 replies • 1070 views
Discussion

ADE corner setup: Can I define a parametric set there?

Category: Custom IC Design

By StephanWeber
•
updated over 2 years ago by Andrew Beckett

4 replies • 8594 views
Discussion

gpdk045 substrate file

Category: Custom IC Design

By SreekanthIISc
•
updated over 2 years ago by Andrew Beckett

1 replies • 6890 views
Discussion

AMD EPYC processors and Cadence support

Category: Custom IC Design

By sysops
•
started over 2 years ago

0 replies • 5943 views
Discussion

open a file and write in it (Verilog-A)

Category: Custom IC Design

By Hagar Hendy
•
updated over 2 years ago by Hagar Hendy

1 replies • 6863 views
Discussion

Trouble with automatic route

Category: Custom IC Design

By TigerLi
•
updated over 2 years ago by TigerLi

1 replies • 6177 views
Discussion

transient noise start time

Category: Custom IC Design

By sjwprcker
•
updated over 2 years ago by sjwprcker

2 replies • 7393 views
Discussion

VerilogA module in a crystal oscillator simulation testbench negatively affects simulation parameters for oscillation

Category: Custom IC Design

By David Mulvihill
•
updated over 2 years ago by David Mulvihill

14 replies • 11324 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.