Digital Implementation

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Min Pulse Width Violation

Category: Digital Implementation

By SG20250716916

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started 4 months ago

0 replies • 1697 views
Discussion

Congestion at Routing Stage

Category: Digital Implementation

By SG20250716916

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started 4 months ago

0 replies • 1741 views
Discussion

Foundation flow stylus

Category: Digital Implementation

By VK20250620161

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started 4 months ago

0 replies • 1705 views
Discussion

INNOVUS: connect internal power nets between hard macros

Category: Digital Implementation

By PK202501238151

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started 4 months ago

0 replies • 1920 views
Discussion

Tracing Gates to RTL Modules and Line Numbers in Flattened Netlist with Genus

Category: Digital Implementation

By SR202412023415

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started 5 months ago

0 replies • 1925 views
Discussion

Synthesizing Specific Gates in Cadence Genus

Category: Digital Implementation

By SR202412023415

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updated 5 months ago by SR202412023415

2 replies • 3132 views
Discussion

Cadence Genus: Submodule synthesis and reuse and integrate it in top module

Category: Digital Implementation

By XH202505277146

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started 6 months ago

0 replies • 2166 views
Discussion

in VSVN netlist getting error , i am using mlcv swicth

Category: Digital Implementation

By SM20250402327

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updated 6 months ago by SM20250402327

1 replies • 2079 views
Discussion

Glitch in Synthesized Netlist Simulation of SR Latch — Occurs Only in One Instance

Category: Digital Implementation

By SaranyaBalan

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started 7 months ago

0 replies • 2344 views
Discussion

querying FSDB

Category: Digital Implementation

By GK20250428557

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started 7 months ago

0 replies • 2241 views
Discussion

Innovus place and route

Category: Digital Implementation

By AB202504284945

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started 7 months ago

0 replies • 3031 views
Discussion

Synthesis Issue: Large Netlist Size Due to Missing Memory Libraries

Category: Digital Implementation

By Ishant Kumar

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started 7 months ago

0 replies • 2159 views
Discussion

Implementation of a PFD circuit

Category: Digital Implementation

By AM202504226619

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started 7 months ago

0 replies • 2308 views
Discussion

report_power vs report_gates

Category: Digital Implementation

By DE202502112928

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started 7 months ago

0 replies • 2213 views
Discussion

How to Build a Clock Tree in Innovus with Buffers at Leaf/Top and Inverters in the Trunk?

Category: Digital Implementation

By BD20250106594

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started 8 months ago

0 replies • 986 views

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