Digital Implementation

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Discussion

Help with Bond Pad & IO Rows Creation.

Category: Digital Implementation

By Tonystark

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updated over 13 years ago by Anjana

1 replies • 849 views
Discussion

Looking for Information on SOCDC-574 Warning

Category: Digital Implementation

By glapi

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started over 13 years ago

0 replies • 12573 views
Discussion

Welcome to the Place and Route Forum

Category: Digital Implementation

By archive

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updated over 13 years ago by wally1

2 replies • 13220 views
Discussion

clock latency

Category: Digital Implementation

By archive

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started over 13 years ago

0 replies • 13229 views
Discussion

Placing bond pads for inline IOs

Category: Digital Implementation

By gops

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updated over 13 years ago by Anjana

1 replies • 13493 views
Discussion

basic queries

Category: Digital Implementation

By sathyarao

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started over 13 years ago

0 replies • 12720 views
Discussion

finding load and driver of net using dbcommands.

Category: Digital Implementation

By KVBABU

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updated over 13 years ago by Kevin P Thomas

1 replies • 13224 views
Discussion

In which file does the Vias widths and heights will be present

Category: Digital Implementation

By kranthiskype

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updated over 13 years ago by crystee

1 replies • 12985 views
Discussion

Encounter as a LEF viewer ?

Category: Digital Implementation

By Anjana

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updated over 13 years ago by Anjana

3 replies • 13995 views
Discussion

Diffrence between (ecoRoute) & (setNanoRouteMode -routeWithEco true) commands

Category: Digital Implementation

By vishwa472

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updated over 13 years ago by vishwa472

2 replies • 2435 views
Discussion

ELC config file

Category: Digital Implementation

By fhagig

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started over 13 years ago

0 replies • 12689 views
Discussion

Ideas for integrating a full-custom designed layout with a semi-custom designed microprocessor.

Category: Digital Implementation

By Thommandram

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updated over 13 years ago by Thommandram

2 replies • 13146 views
Discussion

regarding non default rule of nets and wires

Category: Digital Implementation

By jaya sree

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updated over 13 years ago by wally1

1 replies • 13936 views
Discussion

TieHi term C of inst NAND_X is tied to net SEL_0, which connects to none of the inst's power terms

Category: Digital Implementation

By SomAmbali

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started over 13 years ago

0 replies • 311 views
Discussion

Why Assura extract 2 more pins for each standard cell?

Category: Digital Implementation

By laowang

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started over 13 years ago

0 replies • 12846 views

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