Digital Implementation

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Discussion

LVS problem with standard cells

Category: Digital Implementation

By Medya

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started over 10 years ago

0 replies • 14342 views
Discussion

how to varies the threshold voltage for mos transistor??

Category: Digital Implementation

By vishnu4830

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started over 10 years ago

0 replies • 14062 views
Discussion

Routing Blockage in Lef file

Category: Digital Implementation

By daman

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started over 10 years ago

0 replies • 14540 views
Discussion

ELC failure during simulate stage with status 25600

Category: Digital Implementation

By aggiestudent

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started over 10 years ago

0 replies • 13356 views
Discussion

ELC (Simulation failed with the status 25600)

Category: Digital Implementation

By maple

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updated over 10 years ago by aggiestudent

1 replies • 13638 views
Discussion

encounter selective pin placement

Category: Digital Implementation

By abhishektheone

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started over 10 years ago

0 replies • 13251 views
Discussion

DVFS implementation

Category: Digital Implementation

By mohdirfan

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started over 10 years ago

0 replies • 13184 views
Discussion

Question in APR flow

Category: Digital Implementation

By anasr

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updated over 10 years ago by Kari

1 replies • 16564 views
Discussion

design metrics from saveDesign

Category: Digital Implementation

By mdamunds

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started over 10 years ago

0 replies • 13508 views
Discussion

Warnings during import verilog in Encounter

Category: Digital Implementation

By Ankit01

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updated over 10 years ago by Kari

1 replies • 17325 views
Discussion

EDI saveNetlist gives a Verilog netlist with assign statement

Category: Digital Implementation

By xfan

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updated over 10 years ago by xfan

1 replies • 14954 views
Discussion

CPF style with analog hard macro

Category: Digital Implementation

By GabrielB

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updated over 10 years ago by GabrielB

2 replies • 15539 views
Discussion

report_timing issue

Category: Digital Implementation

By meds7

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updated over 10 years ago by Kari

6 replies • 19299 views
Discussion

Instance a vhdl module inside a verilog file

Category: Digital Implementation

By jsaenznoval

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started over 10 years ago

0 replies • 14354 views
Discussion

Timing analysis Cadence RTL compiler

Category: Digital Implementation

By kenambo

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updated over 10 years ago by grasshopper

2 replies • 14534 views

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