Digital Implementation

Question in APR flow

Category: Digital Implementation

design metrics from saveDesign

Category: Digital Implementation

Warnings during import verilog in Encounter

Category: Digital Implementation

EDI saveNetlist gives a Verilog netlist with assign statement

Category: Digital Implementation

CPF style with analog hard macro

Category: Digital Implementation

report_timing issue

Category: Digital Implementation

Instance a vhdl module inside a verilog file

Category: Digital Implementation

Timing analysis Cadence RTL compiler

Category: Digital Implementation

sroute problems in EDI

Category: Digital Implementation

Spacing several instances of one standard cell using implant spacing rule

Category: Digital Implementation

Custom Clock Tree Routing

Category: Digital Implementation

EPS tool

Category: Digital Implementation

Need guidance to develop a script to get the number of logic levels from an encounter timing report..!

Category: Digital Implementation

How to exclude certain pad pins when using Sroute

Category: Digital Implementation

Is there any tool could estimate the power and time for changing supply voltage in DVFs?

Category: Digital Implementation